LMH6518_15 Datasheet, PDF (33/41 Pages) Texas Instruments – LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier

LMH6518
www.ti.com
SNOSB21C – MAY 2008 – REVISED JULY 2013
For a flat frequency response, the DC (low frequency) gain needs to be lowered to match the less-than-1 V/V AC
(high frequency) path gain through the JFETs. This can be done by increasing the value of R₂.
By choosing the values of R₁₅ and R₁₁ so that
R₂₁
R₁₄
=
R₁₅
R₁₁
(19)
the frequency response at J10 Gate (and consequently the output) will remain flat when C₇ starts to conduct.
Offset correction is done by varying the voltage at R₄, using a DAC or equivalent as shown, in order to shift the
LMH6518 +IN voltage relative to −IN. The result is a circuit which shifts the ground referenced scope input to
2.5V (V_CC/2) CM with adjustable offset and without any JFET or BJT related offsets.
Note that the front-end attenuator (not shown) lower leg resistance should be increased for proper divider-ratio to
account for the 1 MΩ shunt due to the series combination of R₂₁ and R₁₄. For example, a 10:1 front-end
attenuator could be formed by a series 900 kΩ and a shunt 111 kΩ for a scope BNC input impedance of 1 MΩ (=
900K + (111K || 1M)).
Table 8 lists other possible JFET candidates that fall in the range of speed (f_t) and low noise needed:
Company
Interfet
Interfet
Interfet
Interfet
Interfet
Philips
Fairchild
Vishay
Siliconix
Part Number
IF140
IF142
2N5397/8
2N5911/2
J308/9/10
BF513
MMBF5486
Table 8. Suitable JFET Candidates Specifications
V_P (V)
I_dss gm (mS)
(mA)
Input C
(pF)
noise ⁽¹⁾
(nV/RtHz)
−2.2
10
5.5
2.3
4
−2.2
10
5.5
2.3
4
−2.5
13
8
5
2.5
−2.5
13
8
5
2.5
−2.3
21
17
5.8
-3
15
10
5
−4
14
7
4
2.5
SST441
−3.5
13
6
3.5
4
Break
down (V)
−20
−25
−25
−25
−25
−35
Calculated f_t
(MHz)
380
380
254
254
466
318
278
272
(1) Noise data at ∼ I_dss/2
The LNA noise could degrade the scope’s SNR if it is comparable to the input referred noise of the LMH6518.
LNA noise is influenced by the following operating conditions:
a. JFET equivalent input noise
b. BJT Base current
Reducing either “a” or “b” above, or both, reduces noise. One way to reduce “a” is to increase R₈ (currently set to
0Ω). This will reduce the noise impact of J8 but requires a JFET which has a higher I_dss rating in order to
maintain the operating current of J10 so that J10’s noise contribution is minimized. Reducing the BJT Base
current can be accomplished with increasing R₂₀ at the expenses of higher rise/fall times. A higher β will also
reduce the Base current (keep in mind that β and f_t at the operating Collector current is what matters).
Figure 70 shows the impact of the JFET buffer noise on SNR, compared to SNR in Figure 58, assuming either 3
nV/√Hz or 1.5 nV/√Hz buffer noise for comparison:
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