LMH6518_15 Datasheet, PDF (32/41 Pages) Texas Instruments – LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier

LMH6518
SNOSB21C – MAY 2008 – REVISED JULY 2013
APPENDIX A
Here is the schematic drawing for a possible implementation of the LNA buffer shown in Figure 62:
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Scope Input
Input Attenuators
Not Shown
C₆
5 pF
C₇
20 nF
R₂₁
678 k:
R₁₄
322 k:
+
½ U1
LMV842
-
C₃
100 nF
R₂₂
1 M:
+10V
J10
MMBF5486
Q0
BFQ67
R₁₅
678 k:
R₁₁
322 k:
J8
MMBF5486
R₈
0:
R₁₆
20:
R₂₀
500:
C₅
1 nF
R₁₇
100:
LMH6518 +IN
R₄₉
15:
R₂
Adjust R₂ for gain matching
between DC and AC
R₅
500 k:
-10V
-5V
+
½ U1
LMV842
-
+5V
R₀
500 k:
+5V
C₀
1 nF
R₉
200:
R₆
R₅₀
200: 15:
LMH6518 -IN
R₁
500 k:
R₃
500 k:
R₄
500 k:
Offset Control
DAC
Figure 69. JFET LNA Implementation
CIRCUIT OPERATION
This circuit uses an N-Channel JFET (J10) in Source-Follower configuration, to buffer the input signal, with J8
acting as a constant current source. This buffer presents a fixed input impedance (1 MΩ||10 pF) with a gain close
to 1 V/V.
The signal path is AC coupled through C₇ with DC (and low frequency) at LMH6518 +IN maintained through the
action of U1. NPN transistor Q0 is an emitter follower which isolates the buffer from the load (LMH6518 input and
board traces).
The undriven input of the LMH6518, −IN, is biased to 2.5V by R₆, R₉ voltage divider. The Lower ½ of U1 inverts
this voltage and the upper ½ of U1 compares it to the combination of the driven output level at LMH6518 +IN and
the scaled version of scope input at R₁₄, R₂₁ junction, and adjusts J10 Gate accordingly to set the LMH6518 +IN.
This control loop has a frequency response that covers DC to a few Hz, limited by the roll-off capacitor C₃ and
R₁₅ combination (1^st order approximation). DC and low frequency gain is given by:
Gain
(DC)
= ^R14
R₁₄ + R₂₁
§
¨¨¹
©
+
R₅
R₁ || R₂
# _{1 V/V}
(18)
With the values in Figure 69 → R₂ ≈ 452 kΩ:
32
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