LMH6518_15 Datasheet, PDF (27/41 Pages) Texas Instruments – LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier

LMH6518
www.ti.com
SNOSB21C – MAY 2008 – REVISED JULY 2013
2400
R_L = 100:
2200 ^VCM_Aux ^{= 1.2V}
No CM Load
2000 +OUT Aux and -OUT Aux
1800
1600
85°C
25°C
1400
1200
-40°C
1000
4.5 4.7 4.9 5.1 5.3 5.5
V_CC (V)
Figure 63. Auxiliary Output Voltage as a Function of V_CC
LOGIC FUNCTIONS
The following LMH6518 functions are controlled using the SPI-1 compatible bus:
• Filters (20, 100, 200, 350, 650, 750 MHz or full bandwidth)
• Power Mode (Full Power or Auxiliary Hi-Z (high impedance)
• Preamp (HG or LG)
• Attenuation Ladder (0-20 dB, 10 states)
• LMH6518 state “Write” or “Read” back
The SPI-1 bus uses 3.3V logic. “SDIO” is the serial digital input-output which can write to the LMH6518 or read
back from it. “SCLK” is the bus clock with chip select function controlled by “CS”
Pin Name
CS
SCLK
SDIO
Input
Type
Input
Input-Output
SPI-1 PIN DESCRIPTIONS
Function and Connection
Serial Chip Select: While this signal is asserted SCLK is used to accept serial data
present on SDIO and to source serial data on SDIO. When this signal is de-asserted,
SDIO is ignored and SDIO is in TRI-STATE mode.
Serial Clock: Serial data are shifted into and out of the device synchronous with this
clock signal. SCLK transitions with CS de-asserted are ignored. SCLK to be stopped
when not needed to minimize digital crosstalk.
Serial Data-In or Data-out: Serial data are shifted into the device (8 bit Command and 16
bit Data) on this pin while CS signal is asserted during Write operation. Serial data are
shifted out of the device on this pin during a read operation while CS signal is asserted.
At other times, and after one complete Access Cycle (24 bits, see Figure 64 and
Figure 65), this input is ignored. This output is in TRI-STATE mode when CS is de-
asserted. This pin is bi-directional.
Copyright © 2008–2013, Texas Instruments Incorporated
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