LMH6518_15 Datasheet, PDF (23/41 Pages) Texas Instruments – LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier

LMH6518
www.ti.com
SNOSB21C – MAY 2008 – REVISED JULY 2013
The “1.05” factor is to add 5% FS overhead margin to avoid ADC overdrive.
FS_E =
Sx8
10
16.8
x 1.05 x 10²⁰ = 639.3 mV
(13)
Required condition: 0.56V ≤ FS_E ≤ 0.84V
Recommend condition: 0.595V ≤ FS_E ≤ 0.805V for optimum ADC FS
5. Determine the ADC ECM code ratio:
FS_E - 0.56
ECM (ratio) =
0.28
where
• 0.28V= (0.84-0.56)V
• 0.56V is the lower end of the ADC FS adjustability
• For this example:
0.6393 - 0.56
ECM (ratio) =
= 0.283
0.28
(14)
– Required condition: 0 ≤ ECM (ratio) ≤ 1
6. Determine the ECM binary code to be sent on ADC SPI bus:
– Convert the ECM value represented by the ratio calculated above, to binary:
– ECM (binary) = DEC2BIN{ECM(ratio)* 511, 9}
– Where “DEC2BIN” is a spreadsheet function which converts the decimal ECM ratio, from step 5 above,
multiplied by 511 distinct levels, into binary 9 bits.
NOTE
The Web based spreadsheet computes ECM without the use of “DEC2BIN” function to
ease usage by all spreadsheet users who may not have this function installed.
– For this example: ECM (binary) = DEC2BIN(0.283*511, 9) = 010010000. This would be the number to be
sent to the ADC on the SPI bus to program the ADC to the proper FS voltage.
INPUT/OUTPUT CONSIDERATIONS
The LMH6518’s ideal Input/Output Conditions, considered individually, are listed below:
Impedance from
each input to
ground (Ω)
≤50
Table 3. LMH6518's Ideal Input/Output Conditions
Common Mode
Input (V)
Differential Input Load Impedance (Ω) Differential Output
(V_PP)
(V)
1.5 to 3.1
<0.8
100 (differential)/ 50
<0.77
(single ended)
Common Mode
Output (V)
0.95-1.45
In addition to the individual conditions listed in Table 3, the Input/Output terminal conditions should match
differentially (i.e. +IN to −IN and +OUT to −OUT), as well, for best performance.
The input is differential but can be driven single-ended as long as the conditions of Table 3 are met and there is
good matching between the driven and the undriven inputs from DC to the highest frequency of interest. If not,
there could be a settling time impact among other possible performance degradations. The datasheet
specifications are with single-ended input, unless specified. Here is the recommended bench-test schematic to
drive one input and to bias the other input with good matching in mind:
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