THS6204 Datasheet, PDF (31/43 Pages) Texas Instruments – Dual-Port, Differential VDSL2 Line Driver Amplifiers

THS6204
www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
(1) The thermal pad is electrically isolated from all terminals in the package.
Figure 89. Views of Thermally-Enhanced PWP Package (Representative Only—Not to Scale)
THERMAL ANALYSIS
Due to the high output power capability of the
THS6204, heatsinking or forced airflow may be
required under extreme operating conditions.
Maximum desired junction temperature sets the
maximum allowed internal power dissipation as
described below. In no case should the maximum
junction temperature be allowed to exceed +130°C.
Operating junction temperature (T_J) is given by T_A +
P_D × θ_JA. The total internal power dissipation (P_D) is
the sum of quiescent power (P_DQ) and additional
power dissipation in the output stage (P_DL) to deliver
load power. Quiescent power is the specified no-load
supply current times the total supply voltage across
the part. A P_DL depends on the required output signal
and load; using the previously developed model
described in the Total Driver Power for xDSL
Applications section, compute the maximum T_J using
a THS6204 QFN-24 in the circuit of Figure 81
operating at the maximum specified ambient
temperature of +85°C.
Maximum T_J = +85°C + (0.955 ´ 32°C/W) = 115.5°C
(19)
Although this is still well below the specified
maximum junction temperature, system reliability
considerations may require lower tested junction
temperatures. The highest possible internal
dissipation will occur if the load requires current to be
forced into the output for positive output voltages or
sourced from the output for negative output voltages.
This puts a high current through a large internal
voltage drop in the output transistors. The output V-I
plot shown in the Typical Characteristics includes a
boundary for 1W maximum internal power dissipation
under these conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a
high-frequency amplifier like the THS6204 requires
careful attention to board layout parasitic and external
component types. Recommendations that optimize
performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability; on the noninverting input, it can react with
the source impedance to cause unintentional band
limiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of
the ground and power planes around those pins.
Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the
power-supply pins to high-frequency 0.1µF
decoupling capacitors. At the device pins, the ground
and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies
(for bipolar operation) improves second-harmonic
distortion performance. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These
can be placed somewhat farther from the device and
may be shared among several devices in the same
area of the PCB.
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Product Folder Link(s): THS6204
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