THS6204 Datasheet, PDF (28/43 Pages) Texas Instruments – Dual-Port, Differential VDSL2 Line Driver Amplifiers

THS6204
SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 ................................................................................................................................................... www.ti.com
series resistor may be included in the supply lines.
Under heavy output loads this will reduce the
available output voltage swing. A 5Ω series resistor in
each power-supply lead will limit the internal power
dissipation to less than 1W for an output short circuit
while decreasing the available output voltage swing
only 0.5V for up to 100mA desired load currents.
Always place the 0.1µF power-supply decoupling
capacitors after these supply current limiting resistors
directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve the ADC linearity.
A high-speed, high open-loop gain amplifier such as
the THS6204 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
problem have been suggested.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load. This does
not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency.
The additional zero acts to cancel the phase lag from
the capacitive load pole, thus increasing the phase
margin and improving stability. The Typical
Characteristics show the recommended R_S vs
Capacitive Load and the resulting frequency
response at the load. Parasitic capacitive loads
greater than 2pF can begin to degrade the
performance of the THS6204. Long printed-circuit
board (PCB) traces, unmatched cables, and
connections to multiple devices can easily cause this
value to be exceeded. Always consider this effect
carefully, and add the recommended series resistor
as close as possible to the THS6204 output pin (see
the Board Layout Guidelines section).
DISTORTION PERFORMANCE
The THS6204 provides good distortion performance
into a 100Ω load on ±12V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads and/or operation on a
dual ±6V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the second harmonic dominates the distortion with a
negligible third harmonic component. Focusing then
on the second harmonic, increasing the load
impedance improves distortion directly. Remember
that the total load includes the feedback network—in
the noninverting configuration (see Figure 81), this is
the sum of R_F + R_G, whereas in the inverting
configuration it is just R_F. Also, providing an
additional supply decoupling capacitor (0.01µF)
between the supply pins (for bipolar operation)
improves the second-order distortion slightly (3dB to
6dB).
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the second harmonic increasing
at a little less than the expected 2x rate whereas the
third harmonic increases at a little less than the
expected 3x rate. Where the test power doubles, the
difference between it and the second harmonic
decreases less than the expected 6dB, whereas the
difference between it and the third harmonic
decreases by less than the expected 12dB. This also
shows up in the two-tone, third-order intermodulation
spurious (IM3) response curves. The third-order
spurious levels are extremely low at low-output power
levels. The output stage continues to hold them low
even as the fundamental power reaches very high
levels. As the Typical Characteristics show, the
spurious intermodulation powers do not increase as
predicted by a traditional intercept model. As the
fundamental power level increases, the dynamic
range does not decrease significantly.
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