TCM29C13 Datasheet, PDF (3/25 Pages) Texas Instruments – COMBINED SINGLE-CHIP PCM CODEC AND FILTER

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
Terminal Functions
NAME
TERMINAL NO.
TCM29C16
TCM29C13 TCM29C14 TCM29C17 ^I/O
TCM129C13 TCM129C14 TCM129C16
TCM129C17
DESCRIPTION
ANLG GND
16
20
13
Analog ground return for all internal voice circuits. Not internally
connected to DGTL GND.
ANLG IN +
17
21
I Noninverting analog input to uncommitted transmit operational amplifier.
Internally connected to ANLG GND on TCM129C16, TCM29C16,
TCM129C17, and TCM29C17.
ANLG IN –
18
22
14
I Inverting analog input to uncommitted transmit operational amplifier.
ANLG LOOP
7
I Provides loopback test capability. When this input is high, PWRO + is
internally connected to ANLG IN.
CLKR
11
13
9
I Receive master clock and data clock for the fixed-data-rate mode.
Receive master clock only for variable-data-rate mode. CLKR and CLKX
are internally connected together for TCM129C13, TCM129C16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.
CLKSEL
6
6
I Clock-frequency selection. Input must be connected to VBB, VCC, or
ground to reflect the master-clock frequency. When tied to VBB, CLK is
2.048 MHz. When tied to GND, CLK is 1.544 MHz. When tied to VCC,
CLK is 1.536 MHz.
CLKX
11
14
9
I Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable-date-rate mode. CLKR and
CLKX are internally connected for the TCM129C13, TCM129C16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.
DCLKR
7
9
5
I Fixed or variable-data-rate operation select. When connected to VBB,
the device operates in the fixed-data-rate mode. When DCLKR is not
connected to VBB, the device operates in the variable-data-rate mode,
and DCLKR becomes the receiver data clock. DCLKR then operates at
frequencies from 64 kHz to 2.048 MHz.
DGTL GND
10
12
8
Digital ground for all internal logic circuits. Not internally connected to
ANLG GND.
FSR/TSRE
9
11
7
I Frame synchronization clock input/time-slot enable for receive channel.
In the fixed-data-rate mode, FSR distinguishes between signaling and
nonsignaling frames by a double- or single-length pulse, respectively. In
the variable-data-rate mode, this signal must remain high for the duration
of the time slot. The receive channel enters the standby state when FSR
is TTL low for 300 ms.
FSX/TSXE
12
15
10
I Frame-synchronization clock input/time-slot enable for transmit
channel. Operates independently of, but in an analagous manner to,
FSR/TSRE. The transmit channel enters the standby state when FSX is
low for 300 ms.
GSR
4
4
I Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending on the
voltage at GSR.
GSX
19
23
15
O Output terminal of internal uncommitted operational amplifier. Internally,
this is the voice signal input to the transmit filter.
PCM IN
8
10
6
I Receive PCM input. PCM data is clocked in on eight consecutive
negative transitions of the receive data clock, which is CLKR in
fixed-data-rate timing and DCLKR in variable-data-rate timing.
PCM OUT
13
16
11
O Transmit PCM output. PCM data is clocked out on this output on eight
consecutive positive transitions of the transmit data clock, which is CLKX
in fixed-data-rate timing and DCLKX in variable-data-rate timing.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3