TCM29C13 Datasheet, PDF (24/25 Pages) Texas Instruments – COMBINED SINGLE-CHIP PCM CODEC AND FILTER

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
APPLICATION INFORMATION
output gain-set design considerations (see Figure 9)
PWRO+ and PWRO – are low-impedance complementary outputs. The voltages at the nodes are:
V_{O +} at PWRO +
V_{O –} at PWRO –
V_OD = V_{O +} – V_{O –} (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap to the GSR input.
A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and R_L sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
V_A represents the maximum available digital milliwatt output response (V_A = 3.006 Vrms).
VOD = A × VA
1 + (R1/R2)
where A =
4 + (R1/R2)
VO
RL
R1
VOD
R2
2
PWRO+
4
GSR
TCM129C13
TCM129C14
TCM129C16
TCM129C17
TCM29C13
TCM29C14
TCM29C16
TCM29C17
3
PWRO –
PCM IN
VO _–
Digital Milliwatt
Sequence Per
CCITT G. 711
Pin numbers shown are for the TCM29C13, TCM29C14, TCM129C13, and TCM129C14 package only.
Figure 10. Gain-Setting Configuration
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