TCM29C13 Datasheet, PDF (11/25 Pages) Texas Instruments – COMBINED SINGLE-CHIP PCM CODEC AND FILTER

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
PARAMETER
MIN
MAX
td(TSDR)
Time-slot delay time from DCLKR (see Note 9)
140
td(FSR)
Frame-sync delay time
100
tsu(PCM _IN) Setup time before bit 3 falling edge
10
th(PCM _IN) Hold time after bit 4 falling edge
60
tc(DCLKR) Data clock period
488
tSER
Time-slot end receive time
0
NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.
td(DCLKR)–140
tc(CLK)–100
15620
UNIT
ns
ns
ns
ns
ns
ns
64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
tFSLX
tFSLR
tw(DCLK)
PARAMETER
Transmit frame-sync minimum down time
Receive frame-sync minimum down time
Pulse duration, data clock
TEST CONDITIONS
FSX = TTL high for remainder of frame
FSR = TTL high for remainder of frame
MIN
488
1952
MAX
10
UNIT
ns
ns
µs
switching characteristics
propagation delay times over recommended ranges of supply voltage and operating free-air temperature,
fixed-data-rate mode (see Figures 3 and 4)
PARAMETER
From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
tpd1 _{time on time-slot entry) (see Note 10)}
TEST CONDITIONS
CL = 0 to 100 pF
MIN MAX UNIT
0 145 ns
tpd2
From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)
CL = 0 to 100 pF
0 145 ns
tpd3
From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)
CL = 0
tpd4
From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)
CL = 0 to 100 pF
60 215 ns
0 145 ns
tpd5
From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)
CL = 0
60 190 ns
tpd6
From rising edge of channel time slot to SIGR update (TCM129C14 and
TCM29C14 only)
0
2 µs
NOTE 10: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state.
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Note 11 and Figure 5)
PARAMETER
TEST CONDITIONS
MIN MAX UNIT
tpd7 Data delay time from DCLKX
CL = 0 to 100 pF
tpd8 Data delay time from time-slot enable to PCM OUT
CL = 0 to 100 pF
tpd9 Data delay time from time-slot disable to PCM OUT
CL = 0 to 100 pF
tpd10 Data delay time from FSX
td(TSDX) = 80 ns
NOTE 11: Timing parameters tpd8 and tpd9 are referenced to a high-impedance state.
0 100 ns
0
50 ns
0
80 ns
0 140 ns
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