TCM29C13 Datasheet, PDF (10/25 Pages) Texas Instruments – COMBINED SINGLE-CHIP PCM CODEC AND FILTER

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
Gain relative to gain at 1.02 kHz
TEST CONDITIONS
f < 200 Hz
f = 200 Hz
f = 300 Hz to 3 kHz
Input signal at PCM IN is 0 dBm0
f = 3.3 kHz
f = 3.4 kHz
f = 4 kHz
wf 4.6 kHz
MIN
– 0.5
– 0.15
– 0.35
–1
MAX
0.15
0.15
0.15
0.15
– 0.1
– 14
– 30
UNIT
dB
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)
MIN TYP† MAX UNIT
tc(CLK) Clock period for CLKX, CLKR (2.048-MHz systems)
tr, tf
Rise and fall times for CLKX and CLKR
tw(CLK) Pulse duration for CLKX and CLKR (see Note 7)
tw(DCLK) Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz) (see Note 7)
Clock duty cycle, [tw(CLK)/tc(CLK)] for CLKX and CLKR
† _{All typical values are at VBB = – 5 V, VCC = 5 V, and TA = 25°C.}
NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.
488
ns
5
30 ns
220
ns
220
ns
45% 50% 55%
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
td(FSX)
tsu(SIGX)
th(SIGX)
Frame-sync delay time
Setup time before bit 7 falling edge of CLKX (TMC29C14 and TCM129C14 only)
Hold time after bit 8 falling edge of CLKX (TCM29C13 and TCM129C14 only)
MIN
MAX
UNIT
100 tc(CLK) – 100 ns
0
ns
0
ns
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
td(FSR)
tsu(PCM _IN)
th(PCM _IN)
PARAMETER
Frame-sync delay time
Setup time before bit 1 falling edge (TCM129C14 and TCM29C14 only)
Hold time after bit 1 falling edge (TCM129C14 and TCM29C14 only)
MIN
MAX
100 tc(CLK)–100
10
60
UNIT
ns
ns
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 5)
PARAMETER
MIN
MAX
td(TSDX) Time-slot delay time from DCLKX (see Note 8)
140
td(FSX)
Frame-sync delay time
100
tc(DCLKX) Clock period for DCLKX
488
NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation.
td(DCLKX)–140
tc(CLK)–100
15620
UNIT
ns
ns
ns
10
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