BC447 Datasheet, PDF (29/36 Pages) ON Semiconductor – High Voltage Transistors

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In order to achieve the maximum performance of the
device, PCB layout is very critical. Texas Instruments has
developed an EVM for the evaluation of the THS4271 in a
gain of 1. The EVM is shown in Figure 101 through
Figure 104. This EVM is designed to minimize peaking in
the unity gain configuration.
Minimizing the inductance in the feedback path is critical
for reducing the peaking of the frequency response in unity
gain. The recommended maximum inductance allowed in
the feedback path is 4 nH. This can be calculated by using
Equation 8.
ƪ ƫ L(nH)
+ Kȏ
ln
2ȏ
W)
T
)
0.223
W
)
ȏ
T
)
0.5
(8)
where:
W = Width of trace in inches.
ȏ = Length of the trace in inches.
T = Thickness of the trace in inches.
K = 5.08 for dimensions in inches, and K = 2 for dimensions
in cm.
J1
Vin−
J2
Vin+
J9
Power Down
Vs+
R8
R3
R2
C8
R5
R9
Vs+
7 8 _U1
2_{_}
6
R6
3₊
41
Vs −
J4
R7
Vout
Vs −
J8
Power Down Ref
C7
R1
R4
J7
VS−
FB1
C5
C6
J6
GND TP1
VS−
C1
+
VS+
C2 ⁺
J5
VS+
FB2
C3
C4
Figure 95. THS4271/THS4275 EVM Circuit
Configuration
THS4271
THS4275
SLOS397E − JULY 2002 − REVISED JANUARY 2004
Figure 96. THS4271/THS4275 EVM Board
Layout (Top Layer)
Figure 97. THS4271/THS4275 EVM Board
Layout (Second Layer, Ground)
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