BC447 Datasheet, PDF (24/36 Pages) ON Semiconductor – High Voltage Transistors

THS4271
THS4275
SLOS397E − JULY 2002 − REVISED JANUARY 2004
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NOISE ANALYSIS
Driving Capacitive Loads
High slew rate, unity gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate at the
expense of a higher input noise voltage. The 3 nV/√Hz
input voltage noise for the THS4271 and THS4275 is,
however, much lower than comparable amplifiers. The
input-referred voltage noise, and the two input-referred
current noise terms (3 pA/√Hz), combine to give low output
noise under a wide variety of operating conditions.
Figure 87 shows the amplifier noise analysis model with all
the noise terms included. In this model, all noise terms are
taken to be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
ENI
THS4271/THS4275
+
EO
RS
IBN
_
ERS
4kTRS
Rf ^ERF
4kT
Rg
IBI 4kTRf
Rg
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance, which may be
recommended to improve A/D linearity. A high-speed, high
open-loop gain amplifier like the THS4271 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the amplifier’s open-loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. When the primary considerations are
frequency response flatness, pulse response fidelity, or
distortion, the simplest and most effective solution is to
isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
4kT = 1.6E−20J
at 290K
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
Figure 87. Noise Analysis Model
frequency response at the load. Parasitic capacitive loads
greater than 2 pF can begin to degrade the performance
The total output shot noise voltage can be computed as the of the THS4271. Long PC board traces, unmatched
square of all square output noise voltage contributors. cables, and connections to multiple devices can easily
Equation 3 shows the general form for the output noise cause this value to be exceeded. Always consider this
voltage using the terms shown in Figure 87:
effect carefully, and add the recommended series resistor
Ǹǒ Ǔ E_O +
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S NG² ) ^ǒI_BIR_f^Ǔ2 ) 4kTR_fNG
(4) ^{as close as possible to the THS4271 output pin (see Board}
Layout Guidelines).
Dividing this expression by the noise gain (NG=(1+ R_f/R_g))
The criterion for setting this R_(ISO) resistor is a maximum
bandwidth, flat frequency response at the load. For a gain
gives the equivalent input-referred spot noise voltage at
of +2, the frequency response at the output pin is already
the noninverting input, as shown in Equation 4:
slightly peaked without the capacitive load, requiring
Ǹ ǒ Ǔ _{EO +}
2
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S )
I_BIR_f
NG
) ^4kTRf
NG
(5) _{relatively high values of R(ISO) to flatten the response at}
the load. Increasing the noise gain also reduces the
peaking.
Evaluation of these two equations for the circuit and
component values shown in Figure 75 will give a total
output spot noise voltage of 12.2 nV/√Hz and a total
equivalent input spot noise voltage of 6.2 nV/√Hz. This
includes the noise added by the resistors. This total
input-referred spot noise voltage is not much higher than
the 3 nV/√Hz specification for the amplifier voltage noise
alone.
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