BC447 Datasheet, PDF (2/36 Pages) ON Semiconductor – High Voltage Transistors

THS4271
THS4275
SLOS397E − JULY 2002 − REVISED JANUARY 2004
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
UNIT
Supply voltage, V_S
Input voltage, V_I
Output current, I_O
Continuous power dissipation
16.5 V
±V_S
100 mA
See Dissipation Rating Table
Maximum junction temperature, T_J
Maximum junction temperature, continuous
operation, long term reliability T_J ⁽²⁾
Storage temperature range, T_stg
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
150°C
125°C
−65°C to 150°C
300°C
HBM
3000 V
ESD ratings:
CDM
1500 V
MM
1000 V
(1) _{The absolute maximum temperature under any condition is}
limited by the constraints of the silicon process. Stresses above
these ratings may cause permanent damage. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond
those specified is not implied.
(2) _{The maximum junction temperature for continuous operation is}
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE DISSIPATION RATINGS
PACKAGE
D (8 pin)
DGN (8 pin)(3)
θ_JC
(°C/W)
38.3
4.7
θ_JA⁽¹⁾
(°C/W)
97.5
58.4
POWER RATING⁽²⁾
TA ≤ 25°C TA = 85°C
1.02 W 410 mW
1.71 W 685 mW
DGK (8 pin)
54.2
260
385 mW 154 mW
DRB (8 pin)(3)
5
45.8
2.18 W
873 mW
(1) _{This data was taken using the JEDEC standard High-K test PCB.}
(2) _{Power rating is determined with a junction temperature of 125°C.}
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
(3) _{The THS4271/5 may incorporate a PowerPAD on the underside}
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, (VS+ and VS−)
Input common-mode voltage range
Dual supply
Single supply
MIN
±2.5
5
VS− + 1.4
MAX
±7.5
15
VS+ − 1.4
UNIT
V
V
PACKAGING/ORDERING INFORMATION
PLASTIC
SMALL OUTLINE
(D) ⁽¹⁾
ORDERABLE PACKAGE AND NUMBER
LEADLESS MSOP 8 ⁽²⁾
PLASTIC MSOP ⁽¹⁾
PowerPAD
(DRB)
(DGN)
PACKAGE
MARKING
PLASTIC MSOP ⁽¹⁾
(DGK)
PACKAGE
MARKING
THS4271D
THS4271DR
THS4271DRBT
THS4271DRBR
THS4271DGN
THS4271DGNR
BFQ
THS4271DGK
THS4271DGKR
BEY
THS4275D
THS4275DR
THS4275DRBT
THS4275DRBR
THS4275DGN
THS4275DGNR
BFR
THS4275DGK
BJD
THS4275DGKR
(1) _{All packages are available taped and reeled. The R suffix standard quantity is 2500 (e.g., THS4271DGNR).}
(2) _{All packages are available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250 (e.g., THS4271DRBT).}
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