THS1040 Datasheet, PDF (28/32 Pages) Texas Instruments – 3-V, 10-BIT , 40-MSPS CMOS ANALOG TO DIGITAL CONVERTER

THS1040
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
definitions
D Integral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line
drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The
full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the true straight line between these two endpoints.
D Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function
step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last
transition level – first transition level) ÷ (2ⁿ – 2)). Using this definition for DNL separates the effects of gain
and offset error. A minimum DNL better than –1 LSB ensures no missing codes.
D Zero-error—Zero-error is defined as the difference in analog input voltage—between the ideal voltage and
the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is
determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage
corresponding to 1 LSB is found from the difference of top and bottom references divided by the number
of ADC output levels (1024).
D Full-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal
voltage and the actual voltage—that switches the ADC output from code 1022 to code 1023. The ideal
voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level.
The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
D Wake-up time—Wake-up time is from the power-down state to accurate ADC samples being taken and is
specified for MODE = AGND with external reference sources applied to the device at the time of release
of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias
generator, ADC, and SHA.
D Power-up time—Power-up time is from the power-down state to accurate ADC samples being taken and
is specified for MODE = AV_DD/2 or AV_DD and an applied 40-MHz clock. Circuits that need to power up
include VREF reference generation (A1), bias generator, ADC, the SHA, and the on-chip ADC reference
generator (A2).
D Aperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which
the analog input is sampled.
D Aperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay.
28
www.ti.com