THS1040 Datasheet, PDF (17/32 Pages) Texas Instruments – 3-V, 10-BIT , 40-MSPS CMOS ANALOG TO DIGITAL CONVERTER

THS1040
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV_DD or AV_DD/2)
AVDD + VREF
2
AIN+
AIN−
X1 ^Sample
and
X−1 _Hold
ADC
Core
VREF
AGND
Internal
Reference
Buffer
AVDD − VREF
2
Figure 22. ADC Reference Generation, MODE = AV_DD/2
Connecting MODE to AV_DD or AV_DD/2 enables the internal ADC references buffer A2. The outputs of A2 are
connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND. The resulting
voltages at REFT and REFB are:
REFT
+
ǒ_AVDD
)
2
VREF^Ǔ
(7)
REFB
+
ǒ_AVDD
*
2
VREF^Ǔ
(8)
Depending on the connection of the REFSENSE pin, the voltage on VREF may be driven by an off-chip source
or by the internal bandgap reference A1 (see onboard reference generator) to match the THS1040 input range
to their application requirements.
When MODE = AV_DD the BIASREF pin provides a buffered, stabilized AV_DD/2 output voltage that can be used
as a bias reference for ac coupling networks connecting the signal sources to the AIN+ or AIN− inputs. This
removes the need for the user to provide a stabilized external bias reference.
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