BQ24616 Datasheet, PDF (28/34 Pages) Texas Instruments – JEITA Guideline Compatible Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer Battery Charger with System Power Selector and Low Iq

bq24616
SLUSA49A – APRIL 2010 – REVISED MAY 2010
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Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin. ACP/ACN pin needs
to be placed after the input ACFET in order to avoid the over-voltage stress on these pins during hot-plug-in.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
A cost effective and small size solution is shown in Figure 20. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used
for reverse voltage protection for VCC pin ( it can be the body diode of input ACFET). C2 is VCC pin decoupling
capacitor and it should be place to VCC pin as close as possible. The R2 and C2 form a damping RC network to
further protect the IC from high dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can
dominant the equivalent ESR value to get enough damping effect for hot plug-in. R1 and R2 package must be
sized enough to handle inrush current power loss according to resistor manufacturer’s datasheet. The filter
components value always need to be verified with real application and minor adjustments may need to fit in the
real application circuit.
Adapter
connector
D1
R1
2W
C1
2.2 mF
(2010)
R2 ⁽¹²⁰⁶⁾
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 20. Input Filter
PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 21) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
MOSFETs.
3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 22 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route analog ground separately from power ground and use single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground
and power ground together using PowerPAD as the single ground connection point. Or using a 0Ω resistor to
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