BQ34Z100 Datasheet, PDF (27/50 Pages) Texas Instruments – Wide Range Fuel Gauge with Impedance Track™ Technology

bq34z100
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COMMUNICATIONS
SLUSAU1 – MAY 2012
AUTHENTICATION
The bq34z100 can act as a SHA-1/HMAC authentication slave by using its internal engine. Sending a 160-bit
SHA-1 challenge message to the bq34z100 will cause the IC to return a 160-bit digest, based upon the challenge
message and hidden plain-text authentication keys. When this digest matches an identical one, generated by a
host or dedicated authentication master (operating on the same challenge message and using the same plain
text keys), the authentication process is successful.
The bq34z100 contains a default plain-text authentication key of 0x0123456789ABCDEFFEDCBA987654321. If
using the bq34z100 device's internal authentication engine, the default key can be used for development
purposes, but should be changed to a secret key and the part immediately sealed, before putting a pack into
operation.
KEY PROGRAMMING
When the bq34z100 device's SHA-1/HMAC internal engine is used, authentication keys are stored as plain-text
in memory. A plain-text authentication key can only be written to the bq34z100 while the IC is in UNSEALED
mode. Once the IC is UNSEALED, a 0x00 is written to BlockDataControl() to enable the authentication data
commands. Next, subclass ID and offset are specified by writing 0x70 and 0x00 to DataFlashClass() and
DataFlashBlock(), respectively. The bq34z100 is now prepared to receive the 16-byte plain-text key, which must
begin at command location 0x4C. The key is accepted once a successful checksum has been written to
BlockDataChecksum(), for the entire 32-byte block (0x40 through 0x5f), not just the 16-byte key.
EXECUTING AN AUTHENTICATION QUERY
To execute an authentication query in UNSEALED mode, a host must first write 0x01 to the BlockDataControl()
command, to enable the authentication data commands. If in SEALED mode, 0x00 must be written to
DataFlashBlock(), instead.
Next, the host writes a 20-byte authentication challenge to the AuthenticateData() address locations (0x40
through 0x53). After a valid checksum for the challenge is written to AuthenticateChecksum(), the bq34z100 uses
the challenge to perform it own the SHA-1/HMAC computation, in conjunction with its programmed keys. The
resulting digest is written to AuthenticateData(), overwriting the pre-existing challenge. The host may then read
this response and compare it against the result created by its own parallel computation.
HDQ SINGLE-PIN SERIAL INTERFACE
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to
the bq34z100. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted
first. Note that the DATA signal on pin 12 is open-drain and requires an external pull-up resistor. The 8-bit
command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit
7). The R/W field directs the bq34z100 either to
• Store the next 8 or 16 bits of data to a specified register or
• Output 8 or 16 bits of data from the specified register
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
The return-to-one data bit frame of HDQ consists of three distinct sections. The first section is used to start the
transmission by either the host or by the bq34z100 taking the DATA pin to a logic-low state for a time t_STRH,B.
The next section is for data transmission, where the data are valid for a time t_DSU, after the negative edge used
to start communication. The data are held until a time t_DV, allowing the host or bq34z100 time to sample the data
bit. The final section is used to stop the transmission by returning the DATA pin to a logic-high state by at least a
time t_SSU, after the negative edge used to start communication. The final logic-high state is held until the end of
t_CYCH,B, allowing time to ensure the transmission was stopped correctly. The timing for data and break
communication is shown in HDQ COMMUNICATION TIMING CHARACTERISTICS.
HDQ serial communication is normally initiated by the host processor sending a break command to the
bq34z100. A break is detected when the DATA pin is driven to a logic-low state for a time t_B or greater. The
DATA pin should then be returned to its normal ready high logic state for a time t_BR. The bq34z100 is now ready
to receive information from the host processor.
Copyright © 2012, Texas Instruments Incorporated
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