DRV401_15 Datasheet, PDF (24/36 Pages) Texas Instruments – Sensor Signal Conditioning IC for Closed-Loop Magnetic Current Sensor

DRV401
SBVS070B − JUNE 2006 − REVISED MAY 2009
POWER DISSIPATION
Using the thermally-enhanced PowerPAD SO and QFN
packages dramatically reduces the thermal impedance
from junction to case. These packages are constructed
using a down-set lead frame upon which the die is
mounted, as shown in Figure 9a and Figure 9b. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package. Figure 9
shows the SO-20 package as an example. Because this
thermal pad has direct thermal contact with the die,
excellent thermal performance can be achieved by
providing a good thermal path away from the thermal pad.
The two outputs I_COMP1 and I_COMP2 are linear outputs.
Therefore, the power dissipation on each output is
proportional to the current multiplied by the internal voltage
drop on the active transistor. For I_COMP1 and I_COMP2, this
internal voltage drop is the voltage drop to V_DD2 or GND,
according to the current-conducting side of the output.
Output short-circuits are particularly critical for the driver
because the full supply voltage can be seen across the
conducting transistor, and the current is not limited by
anything other than the current density limitation of the
FET. Permanent damage to the device can occur.
The DRV401 does not include temperature protection or
thermal shut-down.
THERMAL PAD
Packages with an exposed thermal pad are specifically
designed to provide excellent power dissipation, but board
layout greatly influences overall heat dissipation. Table 1
shows the thermal resistance (T_JA) for the two packages
with the exposed thermal pad soldered to a normal PCB,
as described in Technical Brief SLMA002, PowerPAD
Thermally-Enhanced Package. See also EIA/JEDEC
www.ti.com
Specifications JESD51-0 to 7, QFN/SON PCB
Attachment (SLUA271), and Quad Flatpack No-Lead
Logic Packages (SCBA017). These documents are
available for download at www.ti.com.
Table 1. q_JA/JP Estimations According To
EIA/JED51-7
q_JP
q_JA Still Air
q_JA with Forced Airflow (150lfm)
QFN-20
9
40
38
SO-20
9
35
32
q_JA = junction-to-ambient thermal resistance,
q_JP = junction-to-pad thermal resistance,
lfm = linear foot per minute.
NOTE: All thermal models have an accuracy ≈ 20%.
Measuring the temperature as close as possible to the
exposed thermal pad is recommended. The relatively low
thermal impedance, q_JP, of less than 10°C/W (with some
additional °C/W to the temperature test point on the PCB)
allows good estimation of the junction temperature in the
application.
The thermal pad on the PCB should contain nine or more
vias for the QFN package. The same applies for the SO
package, where the solder pad on the PCB can be larger
than the exposed pad (for example, 6.6mm × 18mm) as
recommended in the application literature noted
previously.
Component population, layout of traces, layers, and air
flow strongly influence heat dissipation. Worst-case load
conditions should be tested in the real environment to
ensure proper thermal conditions. Minimize thermal stress
for proper long-term operation with a junction temperature
well below +125°C.
DIE
Side View (a)
Exposed
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 9. SO-20 Package Example of Thermally-Enhanced PowerPAD
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