TMS320C6678_15 Datasheet, PDF (236/248 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
8 Revision History
Revision E
Updated EDMA addressing mode descriptions. (Page 160)
Updated BWADJ value setting description in MAIN/DDR3/PASS PLL registers (Page 150)
Added info for output clocks to 1.8-V LVCMOS Signal Transition Levels paragraph (Page 120)
Updated Main PLL and PLL Controller figure: removed /2 label from PLL object (Page 140)
Updated Rise and Fall Transition Time Voltage Reference Levels figure to include label for lower transition (Page 120)
Clarified SmartReflex pin output type (Page 53)
Clarified table caption and first column heading (Page 167)
Corrected SmartReflex peripheral I/O Buffer Type from LVCMOS category to Open drain (Page 119)
Revised Main PLL Clock Input Transition Time figure (Page 152)
Corrected EMIF16 Boot Device Configuration Bit Fields (Page 26)
Added 1.4-GHz support for C6678 device across entire document (Page 1)
Added GYP package to Device Characteristics table (Page 13)
Added GYP package to Mechanical Data Chapter (Page 241)
Restored Parameter Information section (Page 120)
Updated Core Before IO Power Sequencing diagram, changing clock signal SYSCLK1P&N to REFCLK1P&N (Page 123)
Updated IO Before Core Power Sequencing diagram, changing clock signal SYSCLK1P&N to REFCLK1P&N (Page 125)
Updated the PASS PLL Block Diagram (Page 156)
Updated the Trace timing diagram (Page 233)
Updated Parameter Table Index bit field in I2C boot configuration (Page 29)
Updated Parameter Table Index bit field in SPI boot configuration (Page 30)
Updated PKTDMA_PRI_ALLOC register to be CHIP_MSIC_CTL register with new bit field added. (Page 77)
Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings section (Page 38)
Updated slow peripherals in SYSCLK7 description (Page 142)
Updated Chip Select field description in SPI boot device configuration table (Page 30)
Added DSP_SUSP_CTL register section (Page 77)
Revision D
Corrected NMI7-0 from bit fields 23-16 to bit fields 15-8 in LRSTNMIPINSTAT and LRSTNMIPINSTAT_CLR registers (Page 80)
Added Extended Boot Mode table in Boot Device Field section (Page 25)
Updated event PO_VP_SMPSACK_INTR to be Reserved in CIC3 event table (Page 183)
Updated Trace Electrical Timing tables and Timing diagrams (Page 233)
Updated event PO_VCON_SMPSERR_INTR be Reserved in CIC0/1 Event Inputs table (Page 172)
Added Boot Parameter Table section (Page 31)
Added new section DDR3 Memory Controller Race Condition Consideration to include the last 3 paragraphs originally in section 7.11.1
(Page 205)
Added REFCLK description in power sequencing section (Page 122)
Added table of Bootloader section in L2 SRAM in Boot Sequence section (Page 23)
Updated SYSCLK1 to REFCLK in power sequencing section to refer to the clock source of main PLL (Page 123)
Updated note in power sequencing that each supply must ramp monotonically and must reach a stable valid level within 20 ms
(Page 123)
Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffers (Page 151)
Changed all footnote references from CORECLK to SYSCLK1 (Page 231)
Updated PCIe privilege level from "Supervisor" to "Driven by PCIe module" (Page 193)
Corrected "Reserved" to be "Assert local reset to all CorePacs" in LRESET and NMI Decoding table (Page 189)
Added MPU Registers Reset Values section (Page 203)
Added "Initial Startup" row for CVDD in Recommended Operating Conditions table (Page 117)
Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table (Page 76)
Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements table (Page 151)
Corrected tj(CORECLKN/P) max value from 100 to 0.02*tc(CORECLKN/P) (Page 151)
Corrected tj(DDRCLKN/P) max value from 0.025*tc(DDRCLKN/P) to 0.02*tc(DDRCLKN/P) (Page 155)
236 Revision History
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