TMS320C6678_15 Datasheet, PDF (203/248 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
7.11.2.4 MPU Registers Reset Values
Table 7-61 Programmable Range n Registers Reset Values for MPU0
Programmable Start Address
Range
(PROGn_MPSAR)
PROG0
0x01D0_0000
PROG1
0x01F0_0000
PROG2
0x0200_0000
PROG3
0x01E0_0000
PROG4
0x021C_0000
PROG5
0x021F_0000
PROG6
0x0220_0000
PROG7
0x0231_0000
PROG8
0x0232_0000
PROG9
0x0233_0000
PROG10
0x0235_0000
PROG11
0x0240_0000
PROG12
0x0250_0000
PROG13
0x0253_0000
PROG14
0x0260_0000
PROG15
0x0262_0000
End of Table 7-61
MPU0 (Main CFG TeraNet)
End Address
(PROGn_MPEAR)
Memory Page Protection
Attribute (PROGn_MPPA)
0x01D8_03FF
0x03FF_FCB6
0x01F7_FFFF
0x03FF_FC80
0x0209_FFFF
0x03FF_FCB6
0x01EB_FFFF
0x03FF_FCB6
0x021E_0FFF
0x03FF_FC80
0x021F_7FFF
0x03FF_FC80
0x022F_03FF
0x03FF_FCB6
0x0231_03FF
0x03FF_FCB4
0x0232_03FF
0x03FF_FCB4
0x0233_03FF
0x03FF_FCB4
0x0235_0FFF
0x03FF_FCB4
0x024B_3FFF
0x03FF_FCB6
0x0252_03FF
0x03FF_FCB4
0x0254_03FF
0x03FF_FCB6
0x0260_FFFF
0x03FF_FCB4
0x0262_07FF
0x03FF_FCB4
Memory Protection
Tracers
Reserved
NETCP
TSIP
Reserved
Reserved
Timers
PLL
GPIO
SmartReflex
PSC
DEBUG_SS, Tracer Formatters
Reserved
I²C, UART
CICs
Chip-level Registers
Table 7-62 Programmable Range n Registers Reset Values for MPU1
Programmable Start Address
Range
(PROGn_MPSAR)
PROG0
0x3400_0000
PROG1
0x3402_0000
PROG2
0x3406_0000
PROG3
0x3406_8000
PROG4
0x340B_8000
End of Table 7-62
MPU1 (QM_SS DATA PORT)
End Address
(PROGn_MPEAR)
Memory Page Protection
Attribute (PROGn_MPPA)
0x3401_FFFF
0x03FF_FC80
0x3405_FFFF
0x000F_FCB6
0x3406_7FFF
0x03FF_FCB4
0x340B_7FFF
0x03FF_FC80
0x340B_FFFF
0x03FF_FCB6
Memory Protection
Queue Manager subsystem
data
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