AM1810 Datasheet, PDF (221/259 Pages) Texas Instruments – AM1810 ARM Microprocessor For PROFIBUS

AM1810
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SPRS709B – NOVEMBER 2010 – REVISED DECEMBER 2011
5.27 Video Port Interface (VPIF)
The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:
• Up to 2 Video Capture Channels (Channel 0 and Channel 1)
– Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
– Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
– Single Raw Video (8-/10-/12-bit)
• Up to 2 Video Display Channels (Channel 2 and Channel 3)
– Two 8-bit SD Video Display with embedded timing codes (BT.656)
– Single 16-bit HD Video Display with embedded timing codes (BT.1120)
The VPIF capture channel input data format is selectable based on the settings of the specific Channel
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings
of the Channel 0 Control Register.
5.27.1 VPIF Register Descriptions
Table 5-118 shows the VPIF registers.
BYTE ADDRESS
0x01E1 7000
0x01E1 7004
0x01E1 7008
0x01E1 700C
0x01E1 7010
0x01E1 7014 - 0x01E1 701F
0x01E1 7020
0x01E1 7024
0x01E1 7028
0x01E1 702C
0x01E1 7030
0x01E1 7034
0x01E1 7038
0x01E1 703C - 0x01E1 703F
0x01E1 7040
0x01E1 7044
0x01E1 7048
0x01E1 704C
0x01E1 7050
0x01E1 7054
0x01E1 7058
0x01E1 705C
0x01E1 7060
0x01E1 7064
0x01E1 7068
0x01E1 706C
0x01E1 7070
0x01E1 7074
0x01E1 7078
Table 5-118. Video Port Interface (VPIF) Registers
ACRONYM
REGISTER DESCRIPTION
PID
Peripheral identification register
CH0_CTRL
Channel 0 control register
CH1_CTRL
Channel 1 control register
CH2_CTRL
Channel 2 control register
CH3_CTRL
Channel 3 control register
-
Reserved
INTEN
Interrupt enable
INTENSET
Interrupt enable set
INTENCLR
Interrupt enable clear
INTSTAT
Interrupt status
INTSTATCLR
Interrupt status clear
EMU_CTRL
Emulation control
DMA_SIZE
DMA size control
-
Reserved
CAPTURE CHANNEL 0 REGISTERS
CH0_TY_STRTADR
Channel 0 Top Field luma buffer start address
CH0_BY_STRTADR
Channel 0 Bottom Field luma buffer start address
CH0_TC_STRTADR
Channel 0 Top Field chroma buffer start address
CH0_BC_STRTADR
Channel 0 Bottom Field chroma buffer start address
CH0_THA_STRTADR Channel 0 Top Field horizontal ancillary data buffer start address
CH0_BHA_STRTADR Channel 0 Bottom Field horizontal ancillary data buffer start address
CH0_TVA_STRTADR Channel 0 Top Field vertical ancillary data buffer start address
CH0_BVA_STRTADR Channel 0 Bottom Field vertical ancillary data buffer start address
CH0_SUBPIC_CFG
Channel 0 sub-picture configuration
CH0_IMG_ADD_OFST Channel 0 image data address offset
CH0_HA_ADD_OFST Channel 0 horizontal ancillary data address offset
CH0_HSIZE_CFG
Channel 0 horizontal data size configuration
CH0_VSIZE_CFG0
Channel 0 vertical data size configuration (0)
CH0_VSIZE_CFG1
Channel 0 vertical data size configuration (1)
CH0_VSIZE_CFG2
Channel 0 vertical data size configuration (2)
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Peripheral Information and Electrical Specifications 221
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