TMS320C6424_1 Datasheet, PDF (207/245 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347B – MARCH 2007 – REVISED NOVEMBER 2007
6.14.1.3 McASP0 Electrical Data/Timing
6.14.1.3.1 Multichannel Audio Serial Port (McASP) Timing
Table 6-53. Timing Requirements for McASP (see Figure 6-32 and Figure 6-33)⁽¹⁾
NO.
1
t_c(AHCKRX)
2
t_w(AHCKRX)
3
t_c(CKRX)
4
t_w(CKRX)
5
t_su(FRX-CKRX)
6
t_h(CKRX-FRX)
7
t_su(AXR-CKRX)
8
t_h(CKRX-AXR)
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X⁽²⁾
Pulse duration, ACLKR/X high or low
Setup time, AFSR/X input valid before ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
input
ACLKR/X ext
output
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
input
ACLKR/X ext
output
-4/-4Q/-4S
-5/-5Q/-5S
-6
MIN MAX
25
10
25
10
11
3
0
4
6
11
3
3
4
6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
(2) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the McASP0 bit clocks, ACLKR/ACLKX. For
proper device operation, the ACLKR/ACLKX frequency must be no faster than of SYSCLK3 frequency.
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Peripheral Information and Electrical Specifications 207