TMS320C6424_1 Datasheet, PDF (138/245 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347B – MARCH 2007 – REVISED NOVEMBER 2007
CLKMODE
CLKIN
1
OSCIN
0
PLLOUT
PLL
PLLM
PLLEN
1
0
PLLDIV1 (/1)
PLLDIV2 (/3)
PLLDIV3 (/6)
CLKMODE
CLKIN
1
OSCIN
0
OSCDIV1
Figure 6-5. PLL1 Structure Block Diagram
PLL
PLLM
PLLOUT
PLLEN
1
0
PLLDIV1 (/2)
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SYSCLK1
(CLKDIV1 Domain)
SYSCLK2
(CLKDIV3 Domain)
SYSCLK3
(CLKDIV6 Domain)
AUXCLK
(CLKIN Domain)
OBSCLK
(CLKOUT0 Pin)
PLL2_SYSCLK1
(DDR2 PHY)
BPDIV
Figure 6-6. PLL2 Structure Block Diagram
PLL2_SYSCLKBP
(DDR2 VTP)
6.3.5 Power and Sleep Controller (PSC)
The Power and Sleep Controller (PSC) controls power by turning off unused power domains or by gating
off clocks to individual peripherals/modules. The C6424 device only utilizes the clock gating feature of the
PSC for power savings. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each
peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset
control. The LPSCs for C6424 are shown in Table 6-4. The PSC Register memory map is given in
Table 6-5. For more details on the PSC, see the TMS320C642x Power and Sleep Controller (PSC)
Reference Guide (literature number SPRUEN8).
138 Peripheral Information and Electrical Specifications
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