THS12082 Datasheet, PDF (20/38 Pages) Texas Instruments – 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271 – MAY 2000
FIFO trigger level
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13).
If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of
the signal DATA_AV to indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which
can be selected, is dependent on the number of input channels. Either a differential or a single-ended input is
considered as one channel. The processor, therefore, always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3 BIT 2
TRIG1 TRIG0
0
0
0
1
1
0
1
1
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
01
04
08
14
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
02
04
8
12
timing and signal description of the THS12082
The reading from the THS12082 and writing to the THS12082 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS12082 takes place by an internal RD_int signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 10). This signal is then used to strobe the
words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to
become valid will make RD_int active while the write input (WR) is inactive. The first of those external signals going
to its inactive state will then deactivate RD_int again.
Writing to the THS12082 takes place by an internal WR_int signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR
. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal
(either CS0, CS1 or WR) to become valid will make WR_int active while the read input (RD) is inactive. The first
of those external signals going to its inactive state will then deactivate WR_int again.
CS0
Read Enable
CS1
RD
Write Enable
WR
Data Bits
Control/Data
Registers
Figure 10. Logical Combination of CS0, CS1, RD, and WR
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