THS12082 Datasheet, PDF (15/38 Pages) Texas Instruments – 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271 – MAY 2000
reading data from the FIFO (continued)
In Figure 8, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 8. Trigger Level 14 Selected
READ is always the logical combination of CS0, CS1 and RD.
ADC control register
The THS12082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in Table 7.
Table 7. Bit Definitions of Control Register CR0 and CR1
BIT
CR0
CR1
BIT 9
TEST1
RBACK
BIT 8
TEST0
OFFSET
BIT 7
SCAN
BIN/2’s
BIT 6
DIFF1
R/W
BIT 5
DIFF0
DATA_P
BIT 4
CHSEL1
DATA_T
BIT 3
CHSEL0
TRIG1
BIT 2
PD
TRIG0
BIT 1
MODE
OVFL/FRST
BIT 0
VREF
RESET
writing to control register 0 and control register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper data bits D10
and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0
to D9 contain the desired control register value. Table 8 shows the addressing of each control register.
Table 8. Control Register Addressing
D0 – D9
Desired register value
Desired register value
Desired register value
Desired register value
D10/RA0
0
1
0
1
D11/RA1
0
0
1
1
Addressed Control Register
Control register 0
Control register 1
Reserved for future
Reserved for future
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