LMH6624MF Datasheet, PDF (20/31 Pages) Texas Instruments – LMH6624/LMH6626 Single/Dual Ultra Low Noise Wideband Operational Amplifier

LMH6624
SNOSA42F – NOVEMBER 2002 – REVISED MARCH 2013
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Figure 60. Low Noise Magnetic Media Equalizer
Figure 61. Equalizer Frequency Response
LAYOUT CONSIDERATION
TI suggests the copper patterns on the evaluation boards listed below as a guide for high frequency layout.
These boards are also useful as an aid in device testing and characterization. As is the case with all high-speed
amplifiers, accepted-practice RF design technique on the PCB layout is mandatory. Generally, a good high
frequency layout exhibits a separation of power supply and ground traces from the inverting input and output
pins. Parasitic capacitances between these nodes and ground may cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 (SNOA367) for more information). Use high quality chip
capacitors with values in the range of 1000pF to 0.1F for power supply bypassing. One terminal of each chip
capacitor is connected to the ground plane and the other terminal is connected to a point that is as close as
possible to each supply pin as allowed by the manufacturer’s design rules. In addition, connect a tantalum
capacitor with a value between 4.7μF and 10μF in parallel with the chip capacitor. Signal lines connecting the
feedback and gain resistors should be as short as possible to minimize inductance and microstrip line effect.
Place input and output termination resistors as close as possible to the input/output pins. Traces greater than 1
inch in length should be impedance matched to the corresponding load termination.
Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to
minimize the imbalance of amplitude and phase of the differential signal.
Component value selection is another important parameter in working with high speed/high performance
amplifiers. Choosing external resistors that are large in value compared to the value of other critical components
will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board
layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.
Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low
value resistors could load down nodes and will contribute to higher overall power dissipation and high distortion.
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