DRV595 Datasheet, PDF (2/24 Pages) Texas Instruments – 15V/±3A High-Efficiency PWM Power Driver

DRV595
SLOS808 – DECEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SYSTEM BLOCK DIAGRAM
SDZ
Hi-Z
TTL
Buffer
GAIN
OUTP_FB
IN+
Gain
Control
IN–
FAULTZ
OUTPN_FB
Gain
Control
–
+
–
+
–
+
+^–
GVDD
PVCC
Modulation Select
Gate
Drive
+
–
PWM
Logic
GVDD
–
PVCC
+
Gate
Drive
PVCC
BSP
OUTP_FB
OUTP
PVCC
GND
BSN
OUTN_
FB
OUTN
SYNC
GAIN/SLV
FS<2:0>
AVCC
GVDD
PVCC
GND
LDO
Regulator
AVDD
GVDD
PVCC
Ramp
Generator
Biases and
References
SC Detect
Startup Protection
Logic
Thermal
Detect
UVLO/OVLO
GND
Thermal
Pad
2
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