DRV595 Datasheet, PDF (12/24 Pages) Texas Instruments – 15V/±3A High-Efficiency PWM Power Driver

DRV595
SLOS808 – DECEMBER 2012
www.ti.com
START-UP SEQUENCING
To ensure proper operation on power up, wait 10ms after PV_CC and AV_CC are stable before using the analog
inputs, IN– and IN+. Figure 14 illustrates this sequence.
PVCC
AVCC
IN– / IN+
10 ms
Figure 14. Start-Up Sequencing ⁽¹⁾
(1) NOTE: The timing relationship between PVCC assertion and AVCC assertion is not critical.
GAIN SETTING AND MASTER / SLAVE
The gain of the DRV595 is set by the voltage divider connected to the GAIN/SLV control pin. Master or slave
mode is also controlled by the same pin. An internal ADC is used to detect the 4 input states. The first four states
set the DRV595 in Master mode with gains of 20, 26, 32, 36 dB respectively, while the next four states set the
DRV595 in Slave mode with gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up
and cannot be changed while the device is powered. Table 1 shows the recommended resistor values for each
mode and gain combination:
MASTER / SLAVE
MODE
Master
Master
Master
Master
Slave
Slave
Slave
Slave
GAIN
20 dB
26 dB
32 dB
36 dB
20 dB
26 dB
32 dB
36 dB
Table 1. GAIN and MASTER/SLAVE
R1 (to GVDD)
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
R2 (to GND)
20 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
INPUT IMPEDANCE
60 kΩ
30 kΩ
15 kΩ
9 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
2
1
2
1 R1 51 kΩ
R2 51 kΩ
7 _GVDD
8 _GAIN/SLV
9
GND
10
In Master mode, the SYNC terminal is an output, in Slave mode, the SYNC terminal is an input for a clock input.
TTL logic levels with compliance to GVDD.
12
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