THS7319 Datasheet, PDF (18/34 Pages) Texas Instruments – 3-Channel, Very Low Power Video Amplifiers with EDTV Filters and 6-dB Gain

THS7319
SBOS468A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
INPUT OPERATION
The inputs to the THS7319 allow for dc-coupled
inputs. Most DACs or video encoders can be
dc-connected to the THS7319 with essentially any
DAC termination resistance desired for the system.
One of the potential drawbacks to dc-coupling is
when 0 V is applied to the input from the DAC.
Although the input of the THS7319 allows for a 0-V
input signal without issue, the output swing of a
traditional amplifier cannot yield a 0-V signal that
results in possible clipping of the signal. This
limitation is true for any single-supply amplifier
because of the characteristics of the output
transistors. Neither CMOS nor bipolar transistors can
achieve 0 V while sinking current. This transistor
characteristic is also the same reason why the
highest output voltage is always less than the
power-supply voltage when sourcing current.
This output clipping can reduce the sync amplitudes
(both horizontal and vertical sync) on the video
signal. A problem occurs if the video signal receiver
uses an automatic gain control (AGC) loop to account
for losses in the transmission line. Some video AGC
circuits derive gain from the horizontal sync
amplitude. If clipping occurs on the sync amplitude,
then the AGC circuit can increase the gain too
much—resulting in too much luma and/or chroma
amplitude gain correction. This correction may result
in a picture with an overly bright display with too
much color saturation.
Other AGC circuits may use the chroma burst
amplitude for amplitude control. For this situation,
reduction in the sync signals does not alter the proper
gain setting. However, it is good engineering design
practice to ensure that saturation/clipping does not
take place. Transistors always take a finite amount of
time to come out of saturation. This saturation could
possibly result in timing delays or other aberrations
on the signals that may not be desirable.
To eliminate saturation or clipping problems, the
THS7319 has a 150-mV output level shift feature.
This feature takes the input voltage and adds an
internal +75-mV shift to the input signal. Because of
the 6-dB (2 V/V) gain, the resulting output with a 0-V
applied input signal is approximately 150 mV. The
THS7319 rail-to-rail output stage can create this
output level while connected to a typical video load.
This configuration ensures the sync signal clipping or
saturation does not occur. This shift is constant,
regardless of the input signal. The equation for this is
V_OUT = (V_IN × 2 V/V) + 0.15 V. For example, if a 1-V
input is applied, the output is (1 V × 2 V/V) + 0.15 V =
2.15 V.
Because the internal gain is fixed at +6 dB (2 V/V), it
dictates the allowable linear input voltage range. For
example, if the power supply is set to 3 V, the
maximum output is approximately 2.9 V while driving
a significant amount of current. Thus, to avoid
clipping, the allowable input is ([2.9 V – 0.15 V]/2) =
1.375 V. This range is valid for up to the maximum
recommended 5-V power supply that allows
approximately a ([4.9 V – 0.15 V]/2) = 2.375 V input
range while avoiding clipping on the output.
The input impedance of the THS7319 is dictated by
the internal high-impedance unity-gain buffer as
shown in Figure 51. This buffer has a very high
2.4 MΩ || 2 pF input impedance that is effectively
transparent to the source with no interactions. Unlike
other products where the filter elements are tied
directly to the input pin without buffering, there are no
filter performance changes or interaction with the
DAC termination resistance. Note that the internal
voltage shift does not appear at the input pin; it only
shows at the output pin.
While ac-coupling with dc-biasing using external
resistor dividers can be done, it is generally not
recommended because of the large resistor values
required. These large resistor values coupled with the
input bias current of the THS7319 input can cause a
significant voltage shift to appear on the input. If ac
coupling is necessary for a system, several elements
must be taken into account for a proper design: the
high-pass corner frequency (typically desired to be
about 2.5-Hz); the size of the input capacitor value;
the parallel input resistance of the voltage divider;
and the input bias current. Contact Texas Instruments
for design support if ac coupling is necessary in the
design.
+V_S
Input
Pin
Internal
Circuitry
Level
Shift
Figure 51. Equivalent DC Input Mode Circuit
18
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