CC2570 Datasheet, PDF (18/32 Pages) Texas Instruments – 1- and 8-Channel ANT™ RF Network Processors

CC2570
CC2571
SWRS095A – FEBRUARY 2011 – REVISED MARCH 2011
HOST MCU
MESSAGE_READY
SYNC_ENABLE
SRDY
SCLK
SIN
00 100 10 1
SOUT
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ANT
SMSGRDY
SEN
SRDY
SCLK
SOUT
SIN
WRITE FLAG
Figure 14. Synchronous Host-to-ANT Transaction
T0501-01
BIT-SYNCHRONOUS SERIAL INTERFACE
The bit synchronous serial protocol is designed to enable a host MCU to communicate with ANT using GPIO’s
only. The protocol on the host side can be implemented entirely in software, allowing the user to select a very
inexpensive MCU, or to dedicate peripherals to other devices in the system. The difference between the bit
synchronous and the byte synchronous protocol is that the bit synchronous protocol controls the flow of serial
information on a ‘per bit’ level as opposed to ‘per byte’. This means that the SRDY signal will need to be pulsed
for each bit that is to be transported. For this reason the bit synchronous serial protocol will generally be higher
power and lower data rate than the byte synchronous protocol. All other timing and characteristics are the same.
To enable bit synchronous serial communications both the PORTSEL and SFLOW pin should be tied to VCC.
See Figure 15 for hardware setup.
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