CC2570 Datasheet, PDF (17/32 Pages) Texas Instruments – 1- and 8-Channel ANT™ RF Network Processors

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CC2570
CC2571
SWRS095A – FEBRUARY 2011 – REVISED MARCH 2011
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The byte-synchronous protocol provides flow control at the byte level. If the host MCU has a message to send to
the CC257x, it first asserts the SMSGRDY signal to indicate a readiness to communicate. The CC257x responds
by asserting the SEN signal (if it is not already asserted). The host must then pulse the SRDY signal before each
byte is written or read. Note that the first byte is always sent to the host MCU to indicate if ANT is ready to
receive the message (0xA5), or if ANT has a message that it must send (0xA4). In the latter case, the host
should first read out the message from ANT before attempting to send its own message. All bits are sent
LSB-first. The timing for a host-to-ANT transaction is illustrated in Figure 13.
HOST MCU
ANT
MESSAGE_READY
SMSGRDY
SYNC_ENABLE
SEN
SRDY
SRDY
SCLK
SCLK
SIN
10 100 10 1
SOUT
SOUT
SIN
READ FLAG
Figure 13. Synchronous ANT-to-Host Transaction
T0500-01
Whenever ANT has a message to send to the host, it asserts SEN to indicate a readiness to communicate. For
this reason, it is recommended that SEN be connected to an interrupt-capable pin on the host processor, so the
host can be woken up from a sleep state anytime ANT requires communication. An ANT-to-host serial
transaction is very similar to a host-to-ANT transaction. A timing diagram is shown in Figure 14. Once SEN is
detected to be asserted, the host pulses SRDY. The first byte received is 0xA4, indicating that ANT has a
message pending. Subsequent bytes are clocked out following each assertion of the SRDY signal.
Copyright © 2011, Texas Instruments Incorporated
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