DRV8824-Q1_15 Datasheet, PDF (16/30 Pages) Texas Instruments – DRV8824-Q1 Automotive Motor Controller IC

DRV8824-Q1
SLVSCH0 – APRIL 2014
www.ti.com
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize.
The nRESET and nENABLE terminals have internal pulldown resistors of 100 kΩ. The nSLEEP terminal has an
internal pulldown resistor of 1 MΩ.
8.3.6 Protection Circuits
The DRV8824-Q1 is fully protected against undervoltage, overcurrent and overtemperature events.
8.3.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT terminal will be driven low. The device will remain disabled until either nRESET terminal is applied, or
VM is removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the I_SENSE resistor value or VREF voltage.
8.3.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT terminal will
be driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
8.3.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM terminals falls below the undervoltage lockout threshold voltage, all circuitry
in the device will be disabled and internal logic will be reset. Operation will resume when V_M rises above the
UVLO threshold.
8.3.7 Thermal Information
8.3.7.1 Thermal Protection
The DRV8824-Q1 has thermal shutdown (TSD) as described above. If the die temperature exceeds
approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
8.3.7.2 Power Dissipation
Power dissipation in the DRV8824-Q1 is dominated by the power dissipated in the output FET resistance, or
R_DS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
P = 4 R (I )²
TOT
· _DS(ON) · _OUT(RMS)
(2)
where P_TOT is the total power dissipation, R_DS(ON) is the resistance of each FET, and I_OUT(RMS) is the RMS output
current being applied to each winding. I_OUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that R_DS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
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