THS6182_07 Datasheet, PDF (14/35 Pages) Texas Instruments – LOW-POWER DISSIPATION ADSL LINE DRIVER

THS6182
SLLS544G – SEPTEMBER 2002 – REVISED NOVEMBER 2004
3RD HARMONIC DISTORTION
vs
FREQUENCY
−30
−40 ^VCC ^{= ±12 V}
Gain = 5
−50 ^{RL = 50 Ω}
R_F = 1 kΩ
V_O = 2 V_PP
−60
Low Bias
Mid Bias
−70
−80
Full Bias
−90
−100
100 k
Differential configuration
1M
10 M
f − Frequency − Hz
100 M
Figure 59.
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−75
Low Bias
−80
−85
−90
−95
−100
0
Mid Bias
Full Bias
V_CC = ±5 V
Gain = 5
R_L = 200 Ω
R_F = 1 kΩ
f = 1 MHz
5
10
Output Voltage − Vpp
Figure 62.
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
Differential configuration
−75
Low Bias
−80
−85
Mid Bias
−90
−95
−100
0
Full Bias
V_CC = ±5 V
Gain = 5
R_L = 200 Ω
R_F = 1 kΩ
f = 1 MHz
2
4
6
8
10
Output Voltage − Vpp
Figure 65.
3RD HARMONIC DISTORTION
vs
FREQUENCY
−30
Differential configuration
−40
Low Bias
−50
−60
−70 _{Mid Bias}
Full Bias
−80
−90
−100
100 k
V_CC = ±5 V
Gain = 5
R_L 50 Ω
R_F = 1 kΩ
V_O = 2 V_PP
1M
10 M
f − Frequency − Hz
100 M
Figure 60.
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−65
Low Bias
−70
Mid Bias
Full Bias
−75
V_CC = ±12 V
Gain = 5
R_L = 50 Ω
R_F = 1 kΩ
f = 1 MHz
−80
0
5
10
15 20
25 30
Output Voltage − Vpp
Figure 63.
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−70
Differential configuration
−75
Low Bias
−80
−85 Mid Bias
−90
V_CC = ±12 V
Gain = 5
−95
Full Bias
R_L = 200 Ω
R_F = 1 kΩ
f = 1 MHz
−100
0 5 10 15 20 25 30 35 40
Output Voltage − Vpp
Figure 66.
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2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−75
Low Bias
Differential configuration
−80
−85
Mid Bias
−90
−95
−100
0
Full Bias
V_CC = ±12 V
Gain = 5
R_L = 200 Ω
R_F = 1 kΩ
f = 1 MHz
5 10 15 20 25 30 35 40
Output Voltage − Vpp
Figure 61.
2ND HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−65
Low Bias
Differential configuration
−70
Mid Bias
Full Bias
−75
V_CC = ±5 V
Gain = 5
R_L = 50 Ω
R_F = 1 kΩ
f = 1 MHz
−80
0
2
4
6
8
10
Output Voltage − Vpp
Figure 64.
3RD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
−65
−70
Low Bias
−75
V_CC = ±12 V
Gain = 5
R_L = 50 Ω
R_F = 1 kΩ
f = 1 MHz
−80
−85
−90
−95
−100
0
Mid Bias
Full Bias
Differential configuration
5 10 15 20 25 30
Output Voltage − Vpp
Figure 67.
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