LP38869_15 Datasheet, PDF (13/23 Pages) Texas Instruments – 1A FlexCap, Low-Dropout Linear Regulator with 0.75% Accuracy

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V_IN
C_IN
1 PF
ON-
OFF-
IN
OUT
IN
OUT
IN
OUT
IN
OUT
LP38869
RST
SHDN ^SET
SS
GND
C_SS
DAP
LP38869
SNVS877B – AUGUST 2012 – REVISED APRIL 2013
V_OUT
C_OUT
1 PF
R1
RESET
R2
Figure 33. Typical Operating Circuit Adjustable Output Voltage
Soft-Start
As shown in Figure 34, a capacitor on the SS pin allows a gradual ramp-up of the LP38869’s output current,
reducing the initial in-rush current peaks at startup. When SHDN pin is driven low, the soft-start capacitor is
discharged to 0.0V. When the SHDN is driven high, or power is applied to the device, a constant 6.7 µA current
charges the Soft-Start capacitor from 0.0V. The resulting linear ramp voltage on SS increases the current-limit
comparator threshold, limiting the P-channel gate drive. While the voltage on the Soft-Start pin (V_SS) is less than
approximately 300 mV there will be no output current. When Vss rises above approximately 300mV, the output
current limit will rise from zero to approximately 250 mA. As V_SS continues to rise the current limit will also rise
proportionally so that when V_SS is at typically 1.25V the current limit will be at approximately 1A. As the current
limit rises above 1A, the current limit control will pass from V_SS to internal biasing circuitry. See the Soft-Start
Capacitor Selection section for details.
There is a delay time between when SHDN enables the LP38869 and when Soft-Start begins ramping up the
output current limit. This delay time allows the LP38869 internal biasing to fully turn on and settle. The delay time
is set by the time required for the Soft-Start charge current (I_SS) to charge the Soft-Start capacitor from 0.0V to
typically 300 mV. This delay time accounts for approximately 25% of the total Soft-Start time (t_SS). With a 100 nF
Soft-Start capacitor, the delay is approximately 4 ms with the remainder of the t_SS time (approximately 15 ms)
allocated to raising the output current limit from zero to 1A.
Leaving the SS pin floating (open) will disable the Soft-Start feature by setting the t_SS time to zero.
If the current demand from the load is significantly less than 1A, the time needed for the current limit to ramp up
to meet the actual current demand, after the delay time, will be a small fraction of the t_SS time.
Soft-Start Capacitor Selection
Unlike typical Soft-Start circuits that control the rise of the output voltage, the LP38869 Soft-Start controls rise of
the output current limit. The resulting voltage rise across the load will depend on any reactive composition of the
load.
A capacitor (C_SS) connected from the SS pin to GND causes the LP38869’s output current to slowly rise from
zero during start-up, reducing stress on the power path components and input supply. Soft-Start time (t_SS) is
defined as the time from start-up (i.e. t = 0) until the current limit reaches 1A. The current limit will continue to
rise beyond 1A as the SS capacitor continues to charge to a higher voltage.
Typically, the current limit will be at 1A when the voltage on the SS capacitor (Vss) has charged to 1.25V.
The time from start-up (V_SS = 0V) to when the output current limit reaches 1A (V_SS = 1.25V) , can be estimated
by:
t_SS = (C_SS / I_SS) x 1.25V
(3)
This can be simplified to:
t_SS = 0.186 x C_SS
(4)
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