LP38869_15 Datasheet, PDF (12/23 Pages) Texas Instruments – 1A FlexCap, Low-Dropout Linear Regulator with 0.75% Accuracy

LP38869
SNVS877B – AUGUST 2012 – REVISED APRIL 2013
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Input-Output (Drop Out) Voltage
A regulator’s minimum input-to-output voltage differential (dropout voltage) determines the lowest usable input
voltage. In battery-powered systems, this determines the useful end-of-life battery voltage. Since a 200 mΩ P-
channel MOSFET is used as the pass device, dropout voltage is the product of R_DS(ON) and load current passing
through it. The LP38869 operating current remains low in dropout.
For output voltages that are less than the UVLO threshold, the UVLO threshold itself will determine the minimum
input voltage.
Output Voltage Selection
The LP38869 features Dual Mode operation. Connect the SET pin to GND as shown in Figure 32 for the Preset
Mode where the output voltage is preset at the factory. In the Adjustable Mode, set the output voltage between
+0.8V to +5.0V through two external resistors (R1 and R2) connected as a voltage divider to the SET pin as
shown in Figure 33. The output voltage is set by the following equation.
V_OUT = V_REF x (1 + (R1 / R2) )
(1)
where V_REF = 800 mV.
Solving for R1 with a known value for R2:
R1 = R2 x ((V_OUT / V_REF) - 1)
(2)
In the Adjustable Mode the current through R1 and R2 should be much greater than the SET pin bias current to
minimize any error that the bias current may cause. Up to 10 kΩ is acceptable for R2, with R1 scaled for the
appropriate V_OUT.
In the Pre-Set voltage mode, the impedance between the SET pin and ground should be less than 10 kΩ.
Otherwise, spurious conditions could cause the voltage at the SET pin to exceed the typical 87 mV Dual Mode
threshold.
In the Adjustable Mode the resistors used for R1 and R2 should be high quality, tight tolerance, and with
matching temperature coefficients. It is important to remember that, although the value of V_REF is ensured, the
final value of V_OUT in the Adjustable Mode is not. The use of low quality resistors for R1 and R2 can easily
produce an Adjustable Mode V_OUT value that is unacceptable.
Shutdown Mode
A logic low on the SHDN pin disables the LP38869. In shutdown mode, the pass transistor, control circuitry,
reference, and all bias currents are turned off, reducing supply current to typically 2 µA. Connect SHDN to the IN
pin for continuous operation if the function is not needed. In shutdown mode the RST pin is low and the Soft-
Start capacitor is discharged.
RST Comparator
The open-drain RST pin goes low when V_OUT falls 8% below its nominal output voltage. The RST pin remains
low for 3 ms after V_OUT has returned to its normal value. A 100 kΩ pull-up resistor from the RST pin to a suitable
logic supply voltage (typically V_OUT) provides a logic control signal. The RST output logic signal can be used as a
power on-reset signal to a micro-controller, or can drive an external LED for indicating a power failure. The RST
pin is low during shutdown. The RST status remains valid for V_IN as low as 1V. When V_IN is less than 1V the
RST pin status may not be valid.
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