LP38869_15 Datasheet, PDF (11/23 Pages) Texas Instruments – 1A FlexCap, Low-Dropout Linear Regulator with 0.75% Accuracy

LP38869
www.ti.com
SNVS877B – AUGUST 2012 – REVISED APRIL 2013
APPLICATIONS INFORMATION
The LP38869 is a dual mode LDO that operates either as a fixed output, 2.5V regulator, or as an adjustable
output regulator from +0.8V to +5.0V. Output current is specified to be a minimum of 1A. The output requires a
minimum 1µF of capacitance for stability.
Referring to the functional block diagram at Figure 31, the device consists or a 800 mV reference (V_REF), error
amplifier, MOSFET driver, P-channel pass transistor, internal feedback divider, soft-start function, reset timer,
and dual mode comparator, and a low V_OUT (RST) comparator.
With the 800 mV reference connected to the error amplifier’s inverting input, the error amplifier compares this
reference with the selected feedback voltage and amplifies the difference. Usually the feedback voltage is
connected to the error amplifier’s inverting input, but in the case of the LP38869 the logic is inverted to drive a P-
channel MOSFET. The MOSFET driver takes the error amplifier output and applies the appropriate gate drive to
the P-channel transistor. For a high feedback voltage, the MOSFET gate is pulled higher, allowing less current to
flow to the output. The low V_OUT comparator senses when the feedback voltage has dropped 8% below its
expected level, causing RST pin to go low. The Dual Mode comparator monitors the voltage at the SET pin and
selects the feedback path. If the SET pin voltage is below the typical 87 mV threshold, the internal feedback path
is used and the output voltage is regulated to the factory-preset voltage. Otherwise, the output voltage is set with
the external resistor-divider.
Capacitor Selection and Regulator Stability
Capacitors are required at the LP38869’s input and output. Connect a 1 µF or greater capacitor(s) between V_IN
and GND (C_IN), and between V_OUT and GND (C_OUT). Due to the LP38869’s relatively high bandwidth, use only
surface mount ceramic capacitors that have a low equivalent series resistance (ESR) and high self-resonant
frequency (SRF). Make the input and output traces at least 2.5mm wide (the width of the four parallel pins), and
connect C_IN and C_OUT within 6mm of the IC to minimize the impact of PC board trace inductance. The width of
the ground trace should be maximized underneath the IC to ensure a good connection between device pin 10
(GND) and the ground side of the capacitors.
The output capacitor’s ESR and SRF can affect stability and output noise. Use capacitors with a SRF of greater
than 5 MHz and with an ESR of 60 mΩ or less to insure stability and optimum transient response. This is
particularly true in applications with lower output voltage (V_OUT < 2V) and higher output current (I_OUT > 500 mA).
Since some capacitor dielectrics may vary over bias voltage and temperature, consult the capacitor manufacturer
specifications to ensure that the capacitors meet these requirements over all voltage and temperature conditions.
Internal P-Channel Pass Transistor
The LP38869 features a 1A P-channel MOSFET pass transistor. Unlike similar designs using PNP pass
transistors, P-channel MOSFETs require no continuous base (gate) drive, which reduces quiescent current. PNP
based regulators also waste considerable current in dropout when the pass transistor saturates and uses a high
base drive current under large loads. The LP38869 does not suffer from these problems and typically consumes
only 600 uA of quiescent current, even in dropout.
V_IN
C_IN
1 PF
ON-
OFF-
IN
OUT
IN
OUT
IN
OUT
IN
OUT
LP38869
RST
SHDN ^SET
SS
GND
C_SS
DAP
V_OUT
C_OUT
1 PF
RESET
Figure 32. Typical Operating Circuit with Preset Output Voltage
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