AM1802_15 Datasheet, PDF (128/182 Pages) Texas Instruments – AM1802 ARM® Microprocessor

AM1802
SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014
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Table 6-62. Additional⁽¹⁾ SPI1 Master Timings, 5-Pin Option⁽²⁾⁽³⁾ (continued)
NO.
23 t_{d(ENA_SPC)M}
PARAMETER
Delay from assertion of SPI1_ENA
low to first SPI1_CLK edge.⁽¹⁰⁾
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.3V, 1.2V
MIN
MAX
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
1.1V
MIN
MAX
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
1.0V
MIN
MAX
3P+6
UNIT
0.5M+3P+6
ns
3P+6
0.5M+3P+6
Table 6-63. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Enable Option⁽²⁾⁽³⁾
NO.
24
t_{d(SPC_ENAH)S}
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Delay from final SPI1_CLK edge to
slave deasserting SPI1_ENA.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MIN
1.5P-3
1.2V
MAX
2.5P+15
1.1V
MIN
MAX
1.5P-10
2.5P+17
-0.5M+1.5P-3 -0.5M+2.5P+15 -0.5M+1.5P-10 -0.5M+2.5P+17
1.5P-3
2.5P+15
1.5P-10
2.5P+17
-0.5M+1.5P-3 -0.5M+2.5P+15 -0.5M+1.5P-10 -0.5M+2.5P+17
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-59).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
1.0V
MIN
MAX
1.5P-12
2.5P+19
UNIT
-0.5M+1.5P-12 -0.5M+2.5P+19
ns
1.5P-12
2.5P+19
-0.5M+1.5P-12 -0.5M+2.5P+19
Table 6-64. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽²⁾⁽³⁾
NO.
25
t_{d(SCSL_SPC)S}
PARAMETER
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at
slave.
1.3V, 1.2V
MIN
MAX
P+1.5
1.1V
MIN
P+1.5
MAX
1.0V
MIN
P+1.5
MAX
UNIT
ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-59).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
128 Peripheral Information and Electrical Specifications
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