AM1802_15 Datasheet, PDF (10/182 Pages) Texas Instruments – AM1802 ARM® Microprocessor

AM1802
SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014
www.ti.com
Start Address
0x01E2 7000
0x01E2 8000
0x01E2 C000
0x01E2 D000
0x01E3 0000
0x01E3 8000
0x01E3 8400
0x01F0 C000
0x01F0 D000
0x01F0 E000
0x01F0 F000
0x4000 0000
0x6000 0000
0x6200 0000
0x6400 0000
0x6600 0000
0x6800 0000
0x6800 8000
0x8000 0000
0x8002 0000
0xB000 0000
0xB000 8000
0xC000 0000
0xD000 0000
0xFFFD 0000
0xFFFE 0000
0xFFFE E000
0xFFFF 0000
0xFFFF 2000
Table 3-2. AM1802 Top Level Memory Map (continued)
End Address
0x01E2 7FFF
0x01E2 BFFF
0x01E2 CFFF
0x01E2 FFFF
0x01E3 7FFF
0x01E3 83FF
0x01F0 BFFF
0x01F0 CFFF
0x01F0 DFFF
0x01F0 EFFF
0x3FFF FFFF
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x65FF FFFF
0x67FF FFFF
0x6800 7FFF
0x7FFF FFFF
0x8001 FFFF
0xAFFF FFFF
0xB000 7FFF
0xBFFF FFFF
0xCFFF FFFF
0xE000 0000
0xFFFD FFFF
0xFFFE DFFF
0xFFFE FFFF
0xFFFF 1FFF
0xFFFF FFFF
Size
4K
ARM Mem Map
4K
32K
1K
4K
4K
4K
512M
32M
32M
32M
32M
32K
128K
32K
256M
64K
ARM local ROM
8K ARM Interrupt Controller
8K
ARM local RAM
EDMA Mem Map
PSC 1
Master Peripheral Mem Map
SYSCFG1
EDMA3 CC1
EDMA3 TC2
Timer2
Timer3
SPI1
EMIFA SDRAM data (CS0)
EMIFA async data (CS2)
EMIFA async data (CS3)
EMIFA async data (CS4)
EMIFA async data (CS5)
EMIFA Control Regs
On-Chip RAM
DDR2/mDDR Control Regs
DDR2/mDDR Data
10
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