TCA6408_09 Datasheet, PDF (11/31 Pages) Texas Instruments – LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

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TCA6408
LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Reads
The bus master first must send the TCA6408 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the TCA6408 (see Figure 8 and Figure 9).
Data is clocked into the register on the rising edge of the ACK clock pulse.
Slave Address
ACK From
Slave
ACK From
Slave
Slave Address
ACK From
ACK From
Slave ^{Data from Register} Master
S0
1
0
0
0
0
AD
DR
0
A
R/W
Command Byte
A
S0
1
0
0
0
0
AD
DR
1
A
Data
A
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
R/W
First byte
NACK From
Data from Register _Master
Figure 8. Read From Register
Data
Last Byte
NA P
<br/>
SCL
SDA
Read From
Port
Data Into
Port
12 34 5 67 8 9
Slave Address
Data From Port
S0
1 00
0
0
AD
DR
0
A
Data 1
Start
Condition
R/W
ACK From
Slave
Data From Port
A
Data 4
NA P
ACK From
Master
NACK From
Master
Stop
Condition
Data 2
Data 3
t_ph
t_ps
Data 4
Data 5
INT
t_iv
t_ir
A. Transfer of data can be stopped at any time by a stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
input port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
Figure 9. Read Input Port Register
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