THC7984 Datasheet, PDF (6/45 Pages) THine Electronics, Inc. – 10-bit 3-channel Video Signal Digitizer

THC7984_Rev.2.0_E
Sampling Clock Generation
- The THC7984 has PLL to generate the sampling clock from HSYNC. The sampling clock frequency range is from
10MHz to 170 MHz.
- PLL divider ratio (the number of horizontal total pixels per line) can be set to the value between 200 to 8191.
- The sampling clock Phase can be adjusted in 64 steps of T/64.
- The external clock can be used as the sampling clock.
- It is required to set VCO Frequency Range and Charge Pump Current according to the input signal format (resolution) .
Oversampling
- Oversampling is the function that enables sampling analog signals with higher rate than the pixel clock and downsam-
pling to the pixel clock rate with decimation filter, which is effective for improving S/N ratio.
- Oversampling ratio can be selected among 1x (normal operation) , 2x, 4x, and 8x. Even if any is selected, output fre-
quency of the output clock and data is same as normal operation.
Output Clock (DATACK)
- The output clock phase can be selected in 8 steps for the data setup/hold adjustment.
- Divide-by-2 clock can be selected as the output clock for the dual edge data clocking at the subsequent stage. It can not
be selected when oversampling.
SOG Slicer
- Sync on Green (SOG) is sliced at the threshold level above the sync tip to extract the sync signal. The threshold level
can be set by a register ranging from 15 mV to 240 mV in steps of 15mV.
- Low pass filer prior to the slicer can be used to reduce high frequency noise, which can be disabled by a register.
- The slicer also has hysteresis (about 30mV) , which can be disabled by a register.
- 3-level sync signal can be processed by slicing at the pedestal level.
Sync Processor
Sync Processor implements VSYNC separation from CSYNC, vertical timing generation, and detection and measure-
ment of the sync signals. The various automatic sync-processing modes are realized by utilizing the sync detection and
measurement.
The THC7984 can process the copy protection signal.
(1) VSYNC Separation
Extracting VSYNC from Composite sync (CSYNC) or Sync on Green (SOG) .
(2) Vertical Timing Generation
- VSYNC Output Generation
- PLL COAST Generation
- Clamp COAST Generation
- V-Blank of DE Generation
(3) Sync Detection/Measurement
- Input Sync Type Detection (Separate sync, Composite sync, Sync on Green, and No input signal)
- HSYNC, VSYNC Input Polarity Detection
- 3-level Sync Detection
- Interlace Detection
- Vertical Total Line Measurement
- VSYNC Input Pulse Width Measurement
- HSYNC Period Measurement (Reference clock needs to be input into CLAMP pin.)
- SYNC Change Detection
- HSYNC Edge Detection
- Sync Processor IRQ Output
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