THC7984 Datasheet, PDF (18/45 Pages) THine Electronics, Inc. – 10-bit 3-channel Video Signal Digitizer

THC7984_Rev.2.0_E
R02[6:5] Oversampling
Oversampling is the function that enables sampling analog signals with higher rate than the pixel clock and
downsampling to the pixel clock rate with the decimation filter.
When setting it as oversampling, setting of the PLL Divider Ratio (R02 [4:0] /R03 [7:0]) and the Charge Pump Current
(R04 [4:2]) is unnecessary, but it's necessary to change the VCO frequency range (R04 [6:5]) .
Every time the oversampling setting is increased one step, VCO frequency range also must be increased one step.
00b: Normal operation
01b: 2x Oversampling
10b: 4x Oversampling
11b: 8x Oversampling
(ex) In case of 480i (HSYNC Frequency: 15.75kHz / Pixel Clock: 13.51MHz)
Oversampling(R02[6:5])
1x(00b)
2x(01b)
4x(10b)
8x(11b)
VCO Range(R04[6:5])
1/8(00b)
1/4(01b)
1/2(10b)
1/1(11b)
Charge Pump(R04[4:2])
250uA(011b)
250uA(011b)
250uA(011b)
250uA(011b)
* Under the output of 4:4:4 DDR (R1C[7:6]=01b) or 4:2:2 DDR (R1C[7:6]=11b), the oversampling function can't be
used.
* “Internal PLL Divider Ratio” can’t be over 8191.
“Internal PLL Divider Ratio” = PLL Divider Ratio setting * Oversampling setting
* Sampling frequency can’t be over 170MHz
Sampling frequency = Input HSYNC frequency * PLL Divider Ratio * Oversampling setting
* Even if oversampling setting is changed, the output clock frequency and the output data rate don't change.
* The latency of the data output changes according to the oversampling setting.
R02[4:0]/R03[7:0] PLL Divider Ratio
The internal PLL generates sampling clock from HSYNC.
Set the number of horizontal total pixels per line according to the input signal.
*When the external clock input which is supplied through EXTCLK/COAST-pin is used as sampling clock
(R04[1:0]=10b or 11b), PLL Divider Ratio setting is unnecessary.
R04[7] Reserved *Must be set to 1 (Default value: 1)
R04[6:5] VCO Frequency Range *Set according to “Recommended PLL Settings”
R04[4:2] Charge Pump Current *Set according to “Recommended PLL Settings”
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