THC7984 Datasheet, PDF (30/45 Pages) THine Electronics, Inc. – 10-bit 3-channel Video Signal Digitizer

THC7984_Rev.2.0_E
R1C[4:3] Output Clock Select
Select a output signal from DATACK-pin.
00b: Pixel Clock: the same frequency as the sampling clock
01b: 1/2 x Pixel Clock: half the frequency of the sampling clock
10b: Internal Oscillator (approximately 40 MHz)
11b: Reserved
R1C[2:0] Output Clock Phase
Since the output clock phase can be shifted in 8 steps, the setup and hold time of output data can be adjusted.
* If DATACLK is Pixel Clock(R1C[4:3]=00b) , Phase setteing 0-2 is not recommended to use (except for DDR output)
because rising edge of output clock will be around the transition period of output data.
* The phase of internal oscillator clock (R1C[4:3]=10b) can not be controlled.
* When oversampling setting is 8 times, the output clock pahse is possible to set in only 4 steps. (the value of 0 and 1 , 2
and 3, 4 and 5, 6 and 7 will be the same phase setting.)
< DATACK Phase Shift>
Output Data
(Normal Output)
Output Data
(DDR Output)
HO, DE
HO, DE Start Position =Even
DATACK: Pixel Clock
R1C[2:0]=0
R1C[2:0]=1
R1C[2:0]=2
R1C[2:0]=3
R1C[2:0]=4
R1C[2:0]=5
R1C[2:0]=6
R1C[2:0]=7
DATACK: 1/2 x Pixel Clock
R1C[2:0]=0
R1C[2:0]=1
R1C[2:0]=2
R1C[2:0]=3
R1C[2:0]=4
R1C[2:0]=5
R1C[2:0]=6
R1C[2:0]=7
HO, DE Start Position =Odd
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