THC7984 Datasheet, PDF (19/45 Pages) THine Electronics, Inc. – 10-bit 3-channel Video Signal Digitizer

THC7984_Rev.2.0_E
R04[1:0] Sampling Clock Source
Set to 00b, when the internal PLL generates sampling clock (pixel clock) from the HSYNC input.
When an external clock input supplied through EXTCLK/COAST-pin is used and the clock frequency is from 10 to
20MHz, set to 10b.
When an external clock input supplied through EXTCLK/COAST-pin is used and the clock frequency is from 20 to
170MHz, set to 11b.
* Even though the external clock is used as sampling clock(R04[1:0]=10b or 11b) , setting like a Recommended PLL
Settings are necessary.
* When the external clock is used as sampling clock(R04[1:0]=10b or 11b) , PLL COAST and Clamp COAST can not be
input (R16[4]=1, R16[0]=1) .
< Recommended PLL Settings >
480i
480p
720p
1080i
1080p
VGA-60
VGA-72
VGA-75
VGA-85
SVGA-56
SVGA-60
SVGA-72
SVGA-75
SVGA-85
XGA-60
XGA-70
XGA-75
XGA-80
XGA-85
SXGA-60
SXGA-75
SXGA-85
UXGA-60
Hsync
[kHz]
15.750
31.469
45.000
33.750
67.500
31.479
37.861
37.500
43.269
35.156
37.879
48.077
46.875
53.674
48.363
56.476
60.023
64.000
68.677
63.981
79.976
91.146
75.000
Pixel
Rate
13.51
27.00
74.25
74.25
148.50
25.18
31.50
31.50
36.00
36.00
40.00
50.00
49.50
56.25
65.00
75.00
78.75
85.50
94.50
108.00
135.00
157.50
162.00
PLL
Sampling Clock: Internal
Divider R04[6:5] R04[4:2] R04[1:0] R04
858
00
011
00
8C
858
01
011
00
AC
1650
10
101
00
D4
2200
10
100
00
D0
2200
11
101
00
F4
800
01
011
00
AC
832
01
100
00
B0
840
01
100
00
B0
832
01
101
00
B4
1024
01
100
00
B0
1056
01
101
00
B4
1040
10
100
00
D0
1056
10
100
00
D0
1048
10
100
00
D0
1344
10
100
00
D0
1328
10
101
00
D4
1312
10
101
00
D4
1336
11
011
00
EC
1376
11
100
00
F0
1688
11
100
00
F0
1688
11
101
00
F4
1728
11
101
00
F4
2160
11
101
00
F4
Sampling Clock: External
R04[6:5] R04[4:2] R04[1:0] R04
00
000
10
82
01
000
11
A3
10
000
11
C3
10
000
11
C3
11
000
11
E3
01
000
11
A3
01
000
11
A3
01
000
11
A3
01
000
11
A3
01
000
11
A3
01
000
11
A3
10
000
11
C3
10
000
11
C3
10
000
11
C3
10
000
11
C3
10
000
11
C3
10
000
11
C3
11
000
11
E3
11
000
11
E3
11
000
11
E3
11
000
11
E3
11
000
11
E3
11
000
11
E3
* Other than the settings above, please refer to the other document, “THC7984 PLL Setting Sheet”.
R05[5:0] Sampling Clock Phase
The sampling clock phase can be shifted in 64 steps of T/64. Bigger values mean more delay.
* Even the external clock is used as sampling clock(R04[1:0]=10b or 11b) , the clock phase can be shifted.
R06[2:0]/R07[7:0] R-ch (Pr-ch) Gain
R08[2:0]/R09[7:0] G-ch (Y-ch) Gain
R0A[2:0]/R0B[7:0] B-ch (Pb-ch) Gain
The gain can be adjusted from 0.5 to 1.5 in 2048 steps. Bigger value means higher gain.
Gain = (Register Value + 1024) / 2048
Because the full scale of ADC input is 0.7 Vpp (Typical Value) , the gain is set to [0.7 / Video Signal Level*].
* Signal Level without Sync on Video (Vpp)
Example.
Video Signal Level: 0.5 Vpp Gain = 0.7/0.5 =1.4 Register value=1843
Video Signal Level: 0.7 Vpp Gain = 0.7/0.7 =1.0 Register value=1024
Video Signal Level: 1.0 Vpp Gain = 0.7/1.0 =0.7 Register value=410
* The setting method above is not always necessary for the purpose of contrast adjustment. Bigger gain means higher
contrast.
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