THC63LVD827 Datasheet, PDF (4/19 Pages) THine Electronics, Inc. – LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER

THC63LVD827_Rev.1.00_E
Pin Description
Pin Name
TA1+, TA1-
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TCLK1+, TCLK1-
TA2+, TA2-
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
TCLK2+, TCLK2-
R17 ~ R10
G17 ~ G10
B17 ~ B10
DE
VSYNC
HSYNC
CLKIN
Pin #
A1,B1
A2,B2
A3,B3
A5,B5
A4,B4
A6,B6
A7,B7
A8,B8
C9,C8
A9,B9
G1,G2,F1,F2
E1,E2,D1,D2
J4,H4,J3,H3
J2,H2,J1,H1
J8,H8,J7,H7
J6,H6,J5,H5
G9
H9
J9
F9
R/F
G8
RS
F8
Type
Description
LVDS OUT
The 1st Link.
The 1st pixel output data when Dual out.
Output data when Single out.
LVDS OUT LVDS Clock Out for 1st Link.
The 2nd Link.
LVDS OUT
The 2nd pixel output data when Dual out.
LVDS OUT LVDS Clock Out for 2nd Link.
IN
Pixel Data Inputs.
IN
Data Enable Input.
IN
Vsync Input.
IN
Hsync Input.
IN
Clock Input.
Input Clock Triggering Edge Select.
IN
H: Rising edge, L: Falling edge
LVDS swing mode select.
RS
LVDS Swing (VOD, see Fig4 and Fig5)
IN
H
350mV
L
200mV
MAP
LVDS mapping table select. See Fig9 and Fig10.
E8
IN
MAP
H
L
Mapping Mode
Mapping MODE1
Mapping MODE2
Pixel data mode. See Fig7 and Fig8.
MODE
E7
IN
MODE
H
L
Modes
Single out (Single-in/Single-out)
Dual out (Single-in/Dual-out)
Output enable.
O/E
D9
IN
H: Output enable,
L: Output disable (all outputs are Hi-Z).
H: Normal operation,
/PDWN
D8
IN
L: Power down (all outputs are Hi-Z and all circuits are
stand-by mode with minimum current (ITCCS)).
PRBS ^a
C1
IN
Must be tied to GND.
Copyright©2012 THine Electronics, Inc.
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THine Electronics, Inc.