SM8958B Datasheet, PDF (41/49 Pages) SyncMOS Technologies,Inc – 256 bytes SRAM as standard 8052

SM8958B
8-Bit Micro-controller
32KB Flash
& 1KB RAM embedded
Mnemonic Description Dir. Bit 7
WDTC
SCONF
Watchdog
Timer Control
Register
System Control
Register
9FH
BFH
WDTE
WDR
Bit 6 Bit 5
Bit 4
Watchdog Timer
-
CLEAR
-
Bit 3
-
-
-
PDWUE
-
Bit 2 Bit 1 Bit 0 RST
PS [2:0]
00H
-
OME ALEI 02H
Mnemonic: WDTC
Address: 9Fh
7
6
5
4
3
2
1
0
Reset
WDTE -
CLEAR -
-
PS [2:0]
00H
WDTE: Watch Dog Timer enable bit.
CLEAR: Watch Dog Timer clear bit.
If CLEAR bit set to1, setting this bit the Watchdog timer counter clear and re-start to
count from the Beginning.
PS[2:0]: Watch Dog timer over flow period setting.
Mnemonic: SCONF
7
6
5
4
3
WDR
-
-
PDWUE
-
Address: BFh
2
1
0
Reset
-
OME
ALEI
02H
WDR Watch Dog Timer Reset.
When system reset by Watch Dog Timer overflow, WDR will be set to 1.
User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M085
Ver D SM8958B 08/07/2015
- 41 -