SM8958B Datasheet, PDF (38/49 Pages) SyncMOS Technologies,Inc – 256 bytes SRAM as standard 8052

SM8958B
8-Bit Micro-controller
32KB Flash
& 1KB RAM embedded
9. Interrupt
The SM8958B provides 7 interrupt sources with two priority levels. Each source has its own request flag(s) located
in a special function register. Each interrupt requested by the corresponding flag could individually be enabled or
disabled by the enable bits in SFR’s IE.
When the interrupt occurs, the engine will vector to the predetermined address as given in Table 9-1. Once
interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is
terminated by a return from instruction RETI. When an RETI is performed, the processor will return to the
instruction that would have been next when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle,
and then samples are polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled,
then interrupt request flag is set. On the next instruction cycle the interrupt will be acknowledged by hardware
forcing an LCALL to appropriate vector address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the
interrupt occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt
will not be invoked. In other cases, the response time depends on current instruction.
Priority
level
1 (highest)
2
3
4
5
6
7
Table 9-1: Interrupt vectors
Interrupt Request Flags
Interrupt Vector
Address
IE0 – External interrupt 0
0003h
TF0 – Timer 0 interrupt
000Bh
IE1 – External interrupt 1
0013h
TF1 – Timer 1 interrupt
001Bh
RI/TI – Serial channel interrupt
0023h
TF2/EXF2 – Timer 2 interrupt
002Bh
Two Wire Serial Interface
003Bh
Interrupt Number
*(use Keil C Tool)
0
1
2
3
4
5
7
*See Keil C about C51 User’s Guide about Interrupt Function description
Mnemonic Description Dir. Bit 7
IE
Interrupt Enable
Register
A8H
EA
IE1
Interrupt Enable
Register 1
A9H
-
IP
Interrupt Priority
Register
B8H
-
IP1
Interrupt Priority
Register 1
B9H
-
Bit 6 Bit 5
Interrupt
-
ET2
-
-
-
PT2
-
-
Bit 4
ES
-
PS
-
Bit 3
ET1
-
PT1
-
Bit 2 Bit 1 Bit 0 RST
EX1 ET0 EX0 00H
-
ETWSI -
00H
PX1 PT0 PX0 00H
-
PTWSI -
00H
Mnemonic: IE
Address: A8h
7
6
5
4
3
2
1
0
Reset
EA
-
ET2
ES
ET1 EX1 ET0 EX0 00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M085
Ver D SM8958B 08/07/2015
- 38 -