SM5964A Datasheet, PDF (21/30 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded

SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
NAKIF: The Non-acknowledge Interrupt Flag is only set in the master mode when there is no acknowledge bit detected
after one byte data or calling address is transferred.
RXAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has been received after the
complete 8 bits data transmit on the bus.
MASTER: This bit define this module is working at master mode.
TXAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will set (NoAck) or clear (Ack)
and transmit to master to indicate the receive status.
TWSIA ($C1H)
Bit7
Bit6
Bit5
Bit4
Bit3
TWSIA.7 TWSIA.6 TWSIA.5 TWSIA.4 TWSIA.3
TWSIA [7:1]: TWSI Address registers 7 bits.
EXTADDR: Its only compare 4 bits MSB when set this bit.
Bit2
TWSIA.2
Bit1
Bit0
TWSIA.1 EXTADDR
TWSIC1 ($C2H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TWSIE
BusBusy TWSIFS2 TWSIFS1 TWSIFS0
TWSIE: enable TWSI module.
BusBusy: When start condition is detected, this bit will set. When stop condition is detected, this bit will clear.
TWSIFS [2:0]: The TWSI SCL speed divider select.
TWSIFS [2:0]
Speed
000
Xtal/32
001
Xtal/64(default)
010
Xtal/128
011
Xtal/256
100
Xtal/512
101
Xtal/1024
110
Xtal/2048
111
Xtal/4096
TWSIC2 ($C3H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MATCH
SRW
RESTART
MRW
MATCH: When the first received data (following the START signal) in TWSIRxD register is matches with the address
that address register (TWSIA) set, this bit will set.
SRW: The slave mode read (received) or wrote (transmit) on the TWSI bus. When this bit is clear, the slave module
received data on the TWSI bus (SDA).
RESTART: This bit only set by master mode. The master will send a start signal then send TWSIA after the ACK signal
when this bit setting. If TFIF was set (the NonACK signal was received), the master mode will release, and this bit will
clear.
MRW: This bit is determined the data transmit direction. And this bit will transmit to bus as bit0 at Address (Address is
collection TWSIA [7:1] and MRW as 8 bits data). When clear this bit the master is in transmits mode and clear is in
receive mode.
TWSITXD ($C4)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TWSITxD.7 TWSITxD.6 TWSITxD.5 TWSITxD.4 TWSITxD.3 TWSITxD.2 TWSITxD.1 TWSITxD.0
The data written into this register will be automatically downloaded to the shift register when the module
detects a calling address is matched and the bit 0 of the received data is one (Slave transmit mode) or when
the data in the shift register has been transmitted with received acknowledge bit (RXAK) =0 in transmit
Specifications subject to change without notice contact your sales representatives for the most recent information.
21
Ver 2.3 SM5964A 10/2006