SM5964A Datasheet, PDF (17/30 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded

SyncMOS Technologies International, Inc.
SM5964A
Addressing Mode
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
Notes on instruction set and address modes:
Rn
direct
@Ri
#data
#data16
addr11
rel
bit
Register R7-R0 of the currently selected register bank.
8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a SFR
[i.e., I/O port, control register, status register, etc. (128-255)]
8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank
8-bits constant included in the instruction
16-bits constant included in the instruction
11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the same 2
K bytes page of program memory as the first byte of the following instruction.
Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is -128 to
+127 bytes relative to first byte of the following instruction.
Direct addressed bit in internal data RAM or SFR
Mnemonic
Arithmetic Instructions
ADD
A,Rn
ADD
A,direct
ADD
A,@Ri
ADD
A,#data
ADDC
A,Rn
ADDC
A,direct
Table 4: A Summary of the instruction set
OPERATION
A = A + Rn
A = A + direct
A = A + <@Ri>
A = A + #data
A = A + Rn + C
A = A + direct + C
BYTE
1
2
1
2
1
2
CYCLE
1
1
1
1
1
1
ADDC
A,@Ri
A = A + @Ri + C
1
1
ADDC
SUBB
A,#data
A,Rn
A = A + #data + C
A = A － Rn － C
2
1
1
1
SUBB
A,direct
A = A － direct － C
2
1
SUBB
A,@Ri
A = A － <@Ri> － C
1
1
SUBB
A,#data
A = A－#data － C
2
1
INC
A
A=A+1
1
1
INC
Rn
Rn = Rn + 1
1
1
INC
direct
direct = direct + 1
2
1
INC
@Ri
DEC
A
<@Ri> = <@Ri> + 1
A=A － 1
1
1
1
1
DEC
Rn
Rn = Rn － 1
1
1
DEC
direct
direct = direct － 1
2
1
DEC
@Ri
<@Ri> = <@Ri> － 1
1
1
INC
DPTR
DPTR = DPTR － 1
1
2
MUL
AB
B:A = A × B
1
4
DIV
AB
A = INT (A/B)
B = MOD (A/B)
1
4
DA
A
Decimal adjust ACC
1
1
Logical Instructions
ANL
A,Rn
A .AND. Rn
1
1
ANL
A,direct
A .AND. direct
2
1
ANL
A,@Ri
A .AND. <@Ri>
1
1
ANL
A,#data
A .AND. #data
2
1
ANL
direct,A
direct .AND. A
2
1
ANL
direct,#data
direct .AND. #data
3
2
ORL
A,Rn
A .OR. Rn
1
1
ORL
A,direct
A .OR. direct
2
1
ORL
A,@Ri
A .OR. <@Ri>
1
1
ORL
A,#data
A .OR. #data
2
1
ORL
direct,A
direct .OR. A
2
1
ORL
direct,#data
direct .OR. #data
3
2
XRL
A,Rn
A .XOR. Rn
1
1
XRL
A,direct
A .XOR. direct
2
1
XRL
A,@Ri
A .XOR. <@Ri>
1
1
XRL
A,#data
A .XOR. #data
2
1
XRL
direct,A
direct .XOR. A
2
1
XRL
direct,#data
direct .XOR. #data
3
2
CLR
A
A=0
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
17
Ver 2.3 SM5964A 10/2006