SM5964A Datasheet, PDF (13/30 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded

SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
Function Description
The SM5964A is a stand-alone high-performance microcontroller designed for using in 3.3V ISP applications, such as
LCD monitor, instrumentation, or high-end consumer applications.
In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these
applications.
The SM5964A is a control-oriented CPU with on-chip program and data memory. It can be extended with external data
memory up to 64K bytes. For system requiring extra capability, the SM5964A can be enhanced by using external memory
and peripherals.
The SM5964A has two software selectable modes of saving power consumption：IDLE and POWER- DOWN. The IDLE
mode freezes the CPU while allowing the RAM, timer, serial ports and interrupt system to continue functioning. The
POWER-DOWN mode save the RAM contents but freezes the oscillator causing all other chip functions to be inoperative.
The POWER-DOWN mode can be terminated by H/W reset, or by any one of the two external interrupt.
CPU
The CPU of SM5964A is compatible to standard 80C51. The structure of this CPU is shown as FIGURE 12. It contains
Instruction Register (IR), Instruction Decoder, Program Counter (PC), Accumulator (ACC), B Register, and control logic.
This CPU provides a 8-bits bi-direction bus to communicate with other blocks in the chip. The address and data are
transferred through on the same 8-bits bus.
IRQ
RES
Timing & Reset
CLK
CONTROL
LOGIC
TMP2
ACC
TMP1
PROGRAM
ADDR.REGISTER
BUFFER
PROG.
ADDR.
CTRL.
BUS
INSTRUCTION
DECODER
DATA
IN/OUT
INSTRUCTION
REGISTER
SP
B
Register
ALU
PSW
PROGRAM
INCREMENT
PROGRAM
COUNTER
DPTR
PCON
POWER CTRL Signal
Figure 12 The CPU structure
CPU Timing
The machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts for two oscillator
periods. Thus a machine cycle takes 12 oscillator periods. Each state is divided into a PHASE1 half and a PHASE2 half.
FIGURE 13 shows relationships between oscillator, phase, and S1-S6.
Specifications subject to change without notice contact your sales representatives for the most recent information.
13
Ver 2.3 SM5964A 10/2006