SMH4814 Datasheet, PDF (32/44 Pages) Summit Microelectronics, Inc. – Dual Feed Active-ORing Programmable Hot Swap Controller

CONFIGURATION REGISTERS (CONTINUED)
SMH4814
Preliminary Information
Register R02 –Time Slots.
Bits D[7:4] control the Time Slot 1 (time from FB high to second PUP allowed to go active). Bits D[3:0] control the
Time Slot 0 (time from FET fully on to first PUP allowed to go active). See timer table for bit codes.
Register R02
D7 D6 D5 D4 D3 D2 D1 D0
Action
1
0
0
0
X
X
X
X
Time Slot 3 - Time from FB_X high to fourth PUP_X
allowed to go active – 64ms, See Table 3
X
X
X
X
1
0
0
0
Time Slot 2 - Time from FB_X high to third PUP_X
allowed to go active – 64ms, See Table 3
Register R03 –Duty Cycle and Sequence Termination Timers.
Bits D[7:4] control the Duty Cycle Timer (restart time after fault; short circuit detect cycle time; multiply standard times
by 28X). Bits D[3:0] control the Sequence Termination Timer (defines time from PUP active until FB must go high).
Register R03
D7 D6 D5 D4 D3 D2 D1 D0
Action
Duty Cycle Timer – defines the time between when a
Fault occurs and the device attempts to restart the
1
0
1
1
X
X
X
X _{power up sequence. Note that these times are}
actually 28X of that listed in the table.
Sequence Termination Timer – time from when a
X
X
X
X
1
0
0
0 ^{PUP is enabled until its corresponding FB input must}
go high – 64ms, See Table 3
Register R04 –Current Regulation and UV/OV Filter Timers.
Bits D[7:4] control the Subsequent Current Regulation Timer (except for initial power on). Bits D[3:0] control the
UV/OV Filter Timer (when enabled).
Register R04
D7 D6 D5 D4 D3 D2 D1 D0
Action
Current Regulation Timer – defines the amount of
1
0
0
0
X
X
X
X ^{time that the FET can be held in the linear region to}
regulate current to the load – 64ms, See Table 3
UV/OV Filter Time – defines the length of time that
X
X
X
X
1
0
0
0 ^{an under or over voltage condition must be}
sustained to trip the sensor – 64ms, See Table 3
Summit Microelectronics, Inc
2080 2.0 07/21/05
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